arvell.com;
> devicet...@vger.kernel.org; linux-ri...@lists.infradead.org; linux-
> ker...@vger.kernel.org; linux-e...@vger.kernel.org; Sachin Ghadi
>
> Subject: Re: [PATCH 3/3] edac: sifive: Add EDAC support for Memory
> Controller in SiFive SoCs
>
> [External Email] Do not click
> Subject: Re: [PATCH 3/3] edac: sifive: Add EDAC support for Memory Controller
> in SiFive SoCs
Fix subject prefix: "EDAC/sifive: ..."
On Tue, Aug 25, 2020 at 05:36:22PM +0530, Yash Shah wrote:
> Add Memory controller EDAC support in exisiting SiFive platform E
On Tue, 25 Aug 2020 05:06:22 PDT (-0700), yash.s...@sifive.com wrote:
Add Memory controller EDAC support in exisiting SiFive platform EDAC
driver. It registers for notifier events from the SiFive DDR controller
driver for DDR ECC events.
Signed-off-by: Yash Shah
---
drivers/edac/Kconfig
Add Memory controller EDAC support in exisiting SiFive platform EDAC
driver. It registers for notifier events from the SiFive DDR controller
driver for DDR ECC events.
Signed-off-by: Yash Shah
---
drivers/edac/Kconfig | 2 +-
drivers/edac/sifive_edac.c | 117
4 matches
Mail list logo
