Hi,
On Wed, Jan 14, 2015 at 03:08:43PM +0800, Sneeker Yeh wrote:
> Hi Felipe:
>
> thanks for suggestion,
>
> 2015-01-13 1:20 GMT+08:00 Felipe Balbi :
>
> > Hi,
> >
> > On Sun, Jan 11, 2015 at 11:19:55PM +0800, Sneeker Yeh wrote:
> > > > > > enable the quirk only for you. Isn't there a better
Hi,
On Wed, Jan 14, 2015 at 03:08:43PM +0800, Sneeker Yeh wrote:
Hi Felipe:
thanks for suggestion,
2015-01-13 1:20 GMT+08:00 Felipe Balbi ba...@ti.com:
Hi,
On Sun, Jan 11, 2015 at 11:19:55PM +0800, Sneeker Yeh wrote:
enable the quirk only for you. Isn't there a better way of
On Mon, Jan 12, 2015 at 06:29:43PM +0100, Paul Bolle wrote:
> On Mon, 2015-01-12 at 11:20 -0600, Felipe Balbi wrote:
> > On Sun, Jan 11, 2015 at 11:19:55PM +0800, Sneeker Yeh wrote:
> > > in case i express unclearly i also put a pdf:
> > >
On Mon, 2015-01-12 at 11:20 -0600, Felipe Balbi wrote:
> On Sun, Jan 11, 2015 at 11:19:55PM +0800, Sneeker Yeh wrote:
> > in case i express unclearly i also put a pdf:
> > https://drive.google.com/file/d/0B18MmcvvKjNNbDF6eEdHSzZCazA/view
> >
> > This issue is defined by a two-way race at
Hi,
On Sun, Jan 11, 2015 at 11:19:55PM +0800, Sneeker Yeh wrote:
> > > > enable the quirk only for you. Isn't there a better way of enabling the
> > > > quirk based off of revision detection couple with a look on GHWPARAMS*
> > > > registers ?
> > > >
> > > > What's tricking me is this claim that
On Mon, Jan 12, 2015 at 06:29:43PM +0100, Paul Bolle wrote:
On Mon, 2015-01-12 at 11:20 -0600, Felipe Balbi wrote:
On Sun, Jan 11, 2015 at 11:19:55PM +0800, Sneeker Yeh wrote:
in case i express unclearly i also put a pdf:
https://drive.google.com/file/d/0B18MmcvvKjNNbDF6eEdHSzZCazA/view
Hi,
On Sun, Jan 11, 2015 at 11:19:55PM +0800, Sneeker Yeh wrote:
enable the quirk only for you. Isn't there a better way of enabling the
quirk based off of revision detection couple with a look on GHWPARAMS*
registers ?
What's tricking me is this claim that only config-free
On Mon, 2015-01-12 at 11:20 -0600, Felipe Balbi wrote:
On Sun, Jan 11, 2015 at 11:19:55PM +0800, Sneeker Yeh wrote:
in case i express unclearly i also put a pdf:
https://drive.google.com/file/d/0B18MmcvvKjNNbDF6eEdHSzZCazA/view
This issue is defined by a two-way race at disconnect,
Hi,
On Sun, Jan 04, 2015 at 08:55:01PM +0800, Sneeker Yeh wrote:
> > > So far Fujitsu Semiconductor got Synopsys internal case id , that is "
> > > Case: 8000679552".
> > > However the contents belongs this id cannot be referred except Fujitsu
> > > Semiconductor and Synopsys.
> > > Synopsis
Hi,
On Sun, Jan 04, 2015 at 08:55:01PM +0800, Sneeker Yeh wrote:
So far Fujitsu Semiconductor got Synopsys internal case id , that is
Case: 8000679552.
However the contents belongs this id cannot be referred except Fujitsu
Semiconductor and Synopsys.
Synopsis decide the official
Hi,
On Mon, Dec 29, 2014 at 04:07:50PM +0800, Sneeker Yeh wrote:
> Hi,
>
> 2014-12-29 14:41 GMT+08:00 Sneeker Yeh :
>
> > Hi,
> >
> > 2014-12-22 23:37 GMT+08:00 Felipe Balbi :
> >
> >> On Tue, Dec 16, 2014 at 10:10:28AM +0800, Sneeker Yeh wrote:
> >> > Synopsis DesignWare USB3 IP Core
Hi,
On Mon, Dec 29, 2014 at 04:07:50PM +0800, Sneeker Yeh wrote:
Hi,
2014-12-29 14:41 GMT+08:00 Sneeker Yeh sneeker@gmail.com:
Hi,
2014-12-22 23:37 GMT+08:00 Felipe Balbi ba...@ti.com:
On Tue, Dec 16, 2014 at 10:10:28AM +0800, Sneeker Yeh wrote:
Synopsis DesignWare USB3 IP
On Tue, Dec 16, 2014 at 10:10:28AM +0800, Sneeker Yeh wrote:
> Synopsis DesignWare USB3 IP Core integrated with a config-free
> phy needs special handling during device disconnection to avoid
> the host controller dying.
>
> This quirk makes sure PORT_CSC is cleared after the disable slot
>
On Tue, Dec 16, 2014 at 10:10:28AM +0800, Sneeker Yeh wrote:
Synopsis DesignWare USB3 IP Core integrated with a config-free
phy needs special handling during device disconnection to avoid
the host controller dying.
This quirk makes sure PORT_CSC is cleared after the disable slot
command
Synopsis DesignWare USB3 IP Core integrated with a config-free
phy needs special handling during device disconnection to avoid
the host controller dying.
This quirk makes sure PORT_CSC is cleared after the disable slot
command when usb device is disconnected from internal root hub,
otherwise,
Synopsis DesignWare USB3 IP Core integrated with a config-free
phy needs special handling during device disconnection to avoid
the host controller dying.
This quirk makes sure PORT_CSC is cleared after the disable slot
command when usb device is disconnected from internal root hub,
otherwise,
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