addr -= 0x100;
}
@@ -205,8 +213,9 @@ static int amd64_set_scrub_rate(struct
mem_ctl_info *mci, u32 bw)
if (boot_cpu_data.x86 == 0xf)
min_scrubrate = 0x0;
-/* F15h Erratum #505 */
-if (boot_cpu_data.x86 == 0x15)
+/* F15h Models 0x00 - 0x0f Errat
On Tue, Aug 06, 2013 at 05:00:51PM -0500, Aravind Gopalakrishnan wrote:
> Quick question: Shall I change all instances of
> boot_cpu_data.[x86|x86_model] to use pvt->fam and pvt->model wherever
> applicable as part of this patch or have it go in as a separate patch?
Yes, a separate pre-patch would
On 8/6/2013 3:55 PM, Aravind Gopalakrishnan wrote:
On 8/6/2013 3:23 PM, Borislav Petkov wrote:
On Fri, Aug 02, 2013 at 05:43:04PM -0500, Aravind Gopalakrishnan wrote:
Adding support for handling ECC error decoding for new F15 models.
On newer models, support has been included for upto 4 DCT's,
On 8/6/2013 3:23 PM, Borislav Petkov wrote:
On Fri, Aug 02, 2013 at 05:43:04PM -0500, Aravind Gopalakrishnan wrote:
Adding support for handling ECC error decoding for new F15 models.
On newer models, support has been included for upto 4 DCT's,
however, only DCT0 and DCT3 are currently configured
On Fri, Aug 02, 2013 at 05:43:04PM -0500, Aravind Gopalakrishnan wrote:
> Adding support for handling ECC error decoding for new F15 models.
> On newer models, support has been included for upto 4 DCT's,
> however, only DCT0 and DCT3 are currently configured. (Refer BKDG Section
> 2.10)
> There is
Adding support for handling ECC error decoding for new F15 models.
On newer models, support has been included for upto 4 DCT's,
however, only DCT0 and DCT3 are currently configured. (Refer BKDG Section 2.10)
There is also a new "Routing DRAM Requests" algorithm for this model.
Tested on Fam15h M30
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