sys.com;
> jingooh...@gmail.com; robh...@kernel.org; mark.rutl...@arm.com;
> shawn...@kernel.org; Leo Li ;
> lorenzo.pieral...@arm.com; M.h. Lian
> Subject: Re: [PATCH 3/4] ARM: dts: ls1021a: Remove num-lanes property
> from PCIe nodes
>
> On Mon, Aug 12, 2019 at 04:22:27
On Mon, Aug 12, 2019 at 04:22:27AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> On FSL Layerscape SoCs, the number of lanes assigned to PCIe
> controller is not fixed, it is determined by the selected
> SerDes protocol in the RCW (Reset Configuration Word), and
> the PCIe link training is comp
sys.com;
> jingooh...@gmail.com; bhelg...@google.com; robh...@kernel.org;
> mark.rutl...@arm.com; shawn...@kernel.org; Leo Li
> ; lorenzo.pieral...@arm.com; M.h. Lian
>
> Subject: Re: [PATCH 3/4] ARM: dts: ls1021a: Remove num-lanes property
> from PCIe nodes
>
> On Mon, Aug 12
On Mon, Aug 12, 2019 at 04:22:27AM +, Z.q. Hou wrote:
> From: Hou Zhiqiang
>
> On FSL Layerscape SoCs, the number of lanes assigned to PCIe
> controller is not fixed, it is determined by the selected
> SerDes protocol in the RCW (Reset Configuration Word), and
> the PCIe link training is comp
From: Hou Zhiqiang
On FSL Layerscape SoCs, the number of lanes assigned to PCIe
controller is not fixed, it is determined by the selected
SerDes protocol in the RCW (Reset Configuration Word), and
the PCIe link training is completed automatically base on
the selected SerDes protocol, and the link
5 matches
Mail list logo
