Re: [patches] [PATCH 3/4] RISC-V: Flush I$ when making a dirty page executable

2017-11-30 Thread Palmer Dabbelt
On Thu, 30 Nov 2017 12:32:04 PST (-0800), Olof Johansson wrote: Hi, On Mon, Nov 20, 2017 at 10:57 AM, Palmer Dabbelt wrote: From: Andrew Waterman The RISC-V ISA allows for instruction caches that are not coherent WRT stores, even on a single hart. As a result, we need to explicitly flush th

Re: [patches] [PATCH 3/4] RISC-V: Flush I$ when making a dirty page executable

2017-11-30 Thread Olof Johansson
Hi, On Mon, Nov 20, 2017 at 10:57 AM, Palmer Dabbelt wrote: > From: Andrew Waterman > > The RISC-V ISA allows for instruction caches that are not coherent WRT > stores, even on a single hart. As a result, we need to explicitly flush > the instruction cache whenever marking a dirty page as execu

Re: [patches] RE: [PATCH 3/4] RISC-V: Flush I$ when making a dirty page executable

2017-11-22 Thread Andrew Waterman
On Wed, Nov 22, 2017 at 9:38 AM, Palmer Dabbelt wrote: > On Tue, 21 Nov 2017 08:57:07 PST (-0800), david.lai...@aculab.com wrote: >> >> From: Palmer Dabbelt >>> >>> Sent: 20 November 2017 18:58 >>> >>> The RISC-V ISA allows for instruction caches that are not coherent WRT >>> stores, even on a sin

Re: [patches] RE: [PATCH 3/4] RISC-V: Flush I$ when making a dirty page executable

2017-11-22 Thread Palmer Dabbelt
On Tue, 21 Nov 2017 08:57:07 PST (-0800), david.lai...@aculab.com wrote: From: Palmer Dabbelt Sent: 20 November 2017 18:58 The RISC-V ISA allows for instruction caches that are not coherent WRT stores, even on a single hart. As a result, we need to explicitly flush the instruction cache whenev

RE: [PATCH 3/4] RISC-V: Flush I$ when making a dirty page executable

2017-11-21 Thread David Laight
From: Palmer Dabbelt > Sent: 20 November 2017 18:58 > > The RISC-V ISA allows for instruction caches that are not coherent WRT > stores, even on a single hart. As a result, we need to explicitly flush > the instruction cache whenever marking a dirty page as executable in > order to preserve the c

[PATCH 3/4] RISC-V: Flush I$ when making a dirty page executable

2017-11-20 Thread Palmer Dabbelt
From: Andrew Waterman The RISC-V ISA allows for instruction caches that are not coherent WRT stores, even on a single hart. As a result, we need to explicitly flush the instruction cache whenever marking a dirty page as executable in order to preserve the correct system behavior. Local instruct