On Thu, 30 Nov 2017 12:32:04 PST (-0800), Olof Johansson wrote:
Hi,
On Mon, Nov 20, 2017 at 10:57 AM, Palmer Dabbelt wrote:
From: Andrew Waterman
The RISC-V ISA allows for instruction caches that are not coherent WRT
stores, even on a single hart. As a
On Thu, 30 Nov 2017 12:32:04 PST (-0800), Olof Johansson wrote:
Hi,
On Mon, Nov 20, 2017 at 10:57 AM, Palmer Dabbelt wrote:
From: Andrew Waterman
The RISC-V ISA allows for instruction caches that are not coherent WRT
stores, even on a single hart. As a result, we need to explicitly flush
Hi,
On Mon, Nov 20, 2017 at 10:57 AM, Palmer Dabbelt wrote:
> From: Andrew Waterman
>
> The RISC-V ISA allows for instruction caches that are not coherent WRT
> stores, even on a single hart. As a result, we need to explicitly flush
> the instruction cache
Hi,
On Mon, Nov 20, 2017 at 10:57 AM, Palmer Dabbelt wrote:
> From: Andrew Waterman
>
> The RISC-V ISA allows for instruction caches that are not coherent WRT
> stores, even on a single hart. As a result, we need to explicitly flush
> the instruction cache whenever marking a dirty page as
On Wed, Nov 22, 2017 at 9:38 AM, Palmer Dabbelt wrote:
> On Tue, 21 Nov 2017 08:57:07 PST (-0800), david.lai...@aculab.com wrote:
>>
>> From: Palmer Dabbelt
>>>
>>> Sent: 20 November 2017 18:58
>>>
>>> The RISC-V ISA allows for instruction caches that are not coherent WRT
>>>
On Wed, Nov 22, 2017 at 9:38 AM, Palmer Dabbelt wrote:
> On Tue, 21 Nov 2017 08:57:07 PST (-0800), david.lai...@aculab.com wrote:
>>
>> From: Palmer Dabbelt
>>>
>>> Sent: 20 November 2017 18:58
>>>
>>> The RISC-V ISA allows for instruction caches that are not coherent WRT
>>> stores, even on a
On Tue, 21 Nov 2017 08:57:07 PST (-0800), david.lai...@aculab.com wrote:
From: Palmer Dabbelt
Sent: 20 November 2017 18:58
The RISC-V ISA allows for instruction caches that are not coherent WRT
stores, even on a single hart. As a result, we need to explicitly flush
the instruction cache
On Tue, 21 Nov 2017 08:57:07 PST (-0800), david.lai...@aculab.com wrote:
From: Palmer Dabbelt
Sent: 20 November 2017 18:58
The RISC-V ISA allows for instruction caches that are not coherent WRT
stores, even on a single hart. As a result, we need to explicitly flush
the instruction cache
From: Palmer Dabbelt
> Sent: 20 November 2017 18:58
>
> The RISC-V ISA allows for instruction caches that are not coherent WRT
> stores, even on a single hart. As a result, we need to explicitly flush
> the instruction cache whenever marking a dirty page as executable in
> order to preserve the
From: Palmer Dabbelt
> Sent: 20 November 2017 18:58
>
> The RISC-V ISA allows for instruction caches that are not coherent WRT
> stores, even on a single hart. As a result, we need to explicitly flush
> the instruction cache whenever marking a dirty page as executable in
> order to preserve the
From: Andrew Waterman
The RISC-V ISA allows for instruction caches that are not coherent WRT
stores, even on a single hart. As a result, we need to explicitly flush
the instruction cache whenever marking a dirty page as executable in
order to preserve the correct system
From: Andrew Waterman
The RISC-V ISA allows for instruction caches that are not coherent WRT
stores, even on a single hart. As a result, we need to explicitly flush
the instruction cache whenever marking a dirty page as executable in
order to preserve the correct system behavior.
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