From: Dave Hansen
The Intel(R) Xeon Phi(TM) Processor x200 Family (codename: Knights
Landing) has an erratum where a processor thread setting the Accessed
or Dirty bits may not do so atomically against its checks for the
Present bit. This may cause a thread (which is about to page fault)
to set
On 07/03/2016 09:20 PM, Hillf Danton wrote:
...
>> When we have 64-bit PTEs (64-bit mode or 32-bit PAE), we were able
>> to move the swap PTE format around to avoid these troublesome bits.
>> But, 32-bit non-PAE is tight on bits. So, disallow it from running
>> on this hardware. I can't imagine a
>
> The Intel(R) Xeon Phi(TM) Processor x200 Family (codename: Knights
> Landing) has an erratum where a processor thread setting the Accessed
> or Dirty bits may not do so atomically against its checks for the
> Present bit. This may cause a thread (which is about to page fault)
> to set A and/o
The Intel(R) Xeon Phi(TM) Processor x200 Family (codename: Knights
Landing) has an erratum where a processor thread setting the Accessed
or Dirty bits may not do so atomically against its checks for the
Present bit. This may cause a thread (which is about to page fault)
to set A and/or D, even th
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