Quoting Neil Armstrong (2017-03-22 02:22:57)
> On 03/22/2017 12:49 AM, Michael Turquette wrote:
> > Hi Neil,
> >
> > Quoting Neil Armstrong (2017-03-13 06:26:42)
> >> @@ -821,6 +893,7 @@ struct pll_params_table gxbb_gp0_params_table[] = {
> >> &gxbb_hdmi_pll,
> >> &gxbb_sys_pll,
>
On 03/22/2017 12:49 AM, Michael Turquette wrote:
> Hi Neil,
>
> Quoting Neil Armstrong (2017-03-13 06:26:42)
>> @@ -821,6 +893,7 @@ struct pll_params_table gxbb_gp0_params_table[] = {
>> &gxbb_hdmi_pll,
>> &gxbb_sys_pll,
>> &gxbb_gp0_pll,
>> + &gxl_gp0_pll,
Yes, beca
Hi Neil,
Quoting Neil Armstrong (2017-03-13 06:26:42)
> @@ -821,6 +893,7 @@ struct pll_params_table gxbb_gp0_params_table[] = {
> &gxbb_hdmi_pll,
> &gxbb_sys_pll,
> &gxbb_gp0_pll,
> + &gxl_gp0_pll,
Is there a reason for adding the pointer to this array here? It seems
The clock tree in the Amlogic GXBB and GXL/GXM SoCs is shared, but the GXL/GXM
SoCs embeds a different GP0 PLL, and needs different parameters with a vendor
provided reduced rate table.
This patch adds the GXL GP0 variant, and adds a GXL DT compatible in order
to use the GXL GP0 PLL instead of the
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