On 05/07/2016 07:50, Wanpeng Li wrote:
>> > This needs a comment:
>> >
>> > /*
>> > * There are two cases in which execonly is false: 1) for
>> > * non-EPT page tables, in which case we need to set the
>> > * P bit; 2) for EPT page tables where an X-- page
On 05/07/2016 07:50, Wanpeng Li wrote:
>> > This needs a comment:
>> >
>> > /*
>> > * There are two cases in which execonly is false: 1) for
>> > * non-EPT page tables, in which case we need to set the
>> > * P bit; 2) for EPT page tables where an X-- page
2016-06-28 16:57 GMT+08:00 Paolo Bonzini :
>
>
> On 28/06/2016 06:32, Bandan Das wrote:
>> + bool execonly = !(context->guest_rsvd_check.bad_mt_xwr &
>> + (1ull << VMX_EPT_EXECUTABLE_MASK));
>>
>> if (set_mmio_spte(vcpu, sptep, gfn, pfn,
2016-06-28 16:57 GMT+08:00 Paolo Bonzini :
>
>
> On 28/06/2016 06:32, Bandan Das wrote:
>> + bool execonly = !(context->guest_rsvd_check.bad_mt_xwr &
>> + (1ull << VMX_EPT_EXECUTABLE_MASK));
>>
>> if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
>>
On 06/29/2016 04:18 PM, Paolo Bonzini wrote:
On 29/06/2016 05:17, Xiao Guangrong wrote:
+++ b/arch/x86/kvm/mmu.c
@@ -2516,13 +2516,17 @@ static int set_spte(struct kvm_vcpu *vcpu, u64
*sptep,
gfn_t gfn, kvm_pfn_t pfn, bool speculative,
bool can_unsync, bool
On 06/29/2016 04:18 PM, Paolo Bonzini wrote:
On 29/06/2016 05:17, Xiao Guangrong wrote:
+++ b/arch/x86/kvm/mmu.c
@@ -2516,13 +2516,17 @@ static int set_spte(struct kvm_vcpu *vcpu, u64
*sptep,
gfn_t gfn, kvm_pfn_t pfn, bool speculative,
bool can_unsync, bool
On 29/06/2016 05:17, Xiao Guangrong wrote:
>>
>> +++ b/arch/x86/kvm/mmu.c
>> @@ -2516,13 +2516,17 @@ static int set_spte(struct kvm_vcpu *vcpu, u64
>> *sptep,
>> gfn_t gfn, kvm_pfn_t pfn, bool speculative,
>> bool can_unsync, bool host_writable)
>> {
>> -u64
On 29/06/2016 05:17, Xiao Guangrong wrote:
>>
>> +++ b/arch/x86/kvm/mmu.c
>> @@ -2516,13 +2516,17 @@ static int set_spte(struct kvm_vcpu *vcpu, u64
>> *sptep,
>> gfn_t gfn, kvm_pfn_t pfn, bool speculative,
>> bool can_unsync, bool host_writable)
>> {
>> -u64
On 06/28/2016 12:32 PM, Bandan Das wrote:
To support execute only mappings on behalf of L1
hypervisors, we teach set_spte() to honor L1's valid XWR
bits. This is only if host supports EPT execute only. Reuse
ACC_USER_MASK to signify if the L1 hypervisor has the R bit
set
Signed-off-by: Bandan
On 06/28/2016 12:32 PM, Bandan Das wrote:
To support execute only mappings on behalf of L1
hypervisors, we teach set_spte() to honor L1's valid XWR
bits. This is only if host supports EPT execute only. Reuse
ACC_USER_MASK to signify if the L1 hypervisor has the R bit
set
Signed-off-by: Bandan
On 28/06/2016 19:30, Bandan Das wrote:
> Paolo Bonzini writes:
>> On 28/06/2016 06:32, Bandan Das wrote:
>>> + bool execonly = !(context->guest_rsvd_check.bad_mt_xwr &
>>> + (1ull << VMX_EPT_EXECUTABLE_MASK));
>>>
>>> if (set_mmio_spte(vcpu,
On 28/06/2016 19:30, Bandan Das wrote:
> Paolo Bonzini writes:
>> On 28/06/2016 06:32, Bandan Das wrote:
>>> + bool execonly = !(context->guest_rsvd_check.bad_mt_xwr &
>>> + (1ull << VMX_EPT_EXECUTABLE_MASK));
>>>
>>> if (set_mmio_spte(vcpu, sptep, gfn, pfn,
Paolo Bonzini writes:
> On 28/06/2016 06:32, Bandan Das wrote:
>> +bool execonly = !(context->guest_rsvd_check.bad_mt_xwr &
>> + (1ull << VMX_EPT_EXECUTABLE_MASK));
>>
>> if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
>>
Paolo Bonzini writes:
> On 28/06/2016 06:32, Bandan Das wrote:
>> +bool execonly = !(context->guest_rsvd_check.bad_mt_xwr &
>> + (1ull << VMX_EPT_EXECUTABLE_MASK));
>>
>> if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
>> return 0;
>>
>> -
On 28/06/2016 06:32, Bandan Das wrote:
> + bool execonly = !(context->guest_rsvd_check.bad_mt_xwr &
> + (1ull << VMX_EPT_EXECUTABLE_MASK));
>
> if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
> return 0;
>
> - spte = PT_PRESENT_MASK;
>
On 28/06/2016 06:32, Bandan Das wrote:
> + bool execonly = !(context->guest_rsvd_check.bad_mt_xwr &
> + (1ull << VMX_EPT_EXECUTABLE_MASK));
>
> if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access))
> return 0;
>
> - spte = PT_PRESENT_MASK;
>
To support execute only mappings on behalf of L1
hypervisors, we teach set_spte() to honor L1's valid XWR
bits. This is only if host supports EPT execute only. Reuse
ACC_USER_MASK to signify if the L1 hypervisor has the R bit
set
Signed-off-by: Bandan Das
---
arch/x86/kvm/mmu.c
To support execute only mappings on behalf of L1
hypervisors, we teach set_spte() to honor L1's valid XWR
bits. This is only if host supports EPT execute only. Reuse
ACC_USER_MASK to signify if the L1 hypervisor has the R bit
set
Signed-off-by: Bandan Das
---
arch/x86/kvm/mmu.c | 9
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