On 30/05/17 16:25, Thomas Petazzoni wrote:
> Hello,
>
> On Tue, 30 May 2017 16:17:41 +0100, Marc Zyngier wrote:
>
>>> Indeed. But do we care? Can an edge interrupt be left pending from the
>>> firmware?
>>
>> I cannot see why not. It is just as likely as a level interrupt.
>
> OK.
>
>>> I'm
On 30/05/17 16:25, Thomas Petazzoni wrote:
> Hello,
>
> On Tue, 30 May 2017 16:17:41 +0100, Marc Zyngier wrote:
>
>>> Indeed. But do we care? Can an edge interrupt be left pending from the
>>> firmware?
>>
>> I cannot see why not. It is just as likely as a level interrupt.
>
> OK.
>
>>> I'm
Hello,
On Tue, 30 May 2017 16:17:41 +0100, Marc Zyngier wrote:
> > Indeed. But do we care? Can an edge interrupt be left pending from the
> > firmware?
>
> I cannot see why not. It is just as likely as a level interrupt.
OK.
> > I'm not sure how to use this irq_set_irqchip_state() API. I
Hello,
On Tue, 30 May 2017 16:17:41 +0100, Marc Zyngier wrote:
> > Indeed. But do we care? Can an edge interrupt be left pending from the
> > firmware?
>
> I cannot see why not. It is just as likely as a level interrupt.
OK.
> > I'm not sure how to use this irq_set_irqchip_state() API. I
On 30/05/17 15:54, Thomas Petazzoni wrote:
> Hello,
>
> On Tue, 30 May 2017 14:55:57 +0100, Marc Zyngier wrote:
>
>>> + for (i = 0; i < GICP_INT_COUNT; i++)
>>> + writel(i, regs + GICP_CLRSPI_NSR_OFFSET);
>>
>> What does this do on an edge interrupt?
>
> I guess nothing. What the
On 30/05/17 15:54, Thomas Petazzoni wrote:
> Hello,
>
> On Tue, 30 May 2017 14:55:57 +0100, Marc Zyngier wrote:
>
>>> + for (i = 0; i < GICP_INT_COUNT; i++)
>>> + writel(i, regs + GICP_CLRSPI_NSR_OFFSET);
>>
>> What does this do on an edge interrupt?
>
> I guess nothing. What the
Hello,
On Tue, 30 May 2017 14:55:57 +0100, Marc Zyngier wrote:
> > + for (i = 0; i < GICP_INT_COUNT; i++)
> > + writel(i, regs + GICP_CLRSPI_NSR_OFFSET);
>
> What does this do on an edge interrupt?
I guess nothing. What the ICU does is:
* For level interrupts: when the
Hello,
On Tue, 30 May 2017 14:55:57 +0100, Marc Zyngier wrote:
> > + for (i = 0; i < GICP_INT_COUNT; i++)
> > + writel(i, regs + GICP_CLRSPI_NSR_OFFSET);
>
> What does this do on an edge interrupt?
I guess nothing. What the ICU does is:
* For level interrupts: when the
On 30/05/17 10:16, Thomas Petazzoni wrote:
> This commit adds a simple driver for the Marvell GICP, a hardware unit
> that converts memory writes into GIC SPI interrupts. The driver doesn't
> do anything but clear all interrupts at boot time, to avoid spurious
> interrupts left by the firmware.
>
On 30/05/17 10:16, Thomas Petazzoni wrote:
> This commit adds a simple driver for the Marvell GICP, a hardware unit
> that converts memory writes into GIC SPI interrupts. The driver doesn't
> do anything but clear all interrupts at boot time, to avoid spurious
> interrupts left by the firmware.
>
This commit adds a simple driver for the Marvell GICP, a hardware unit
that converts memory writes into GIC SPI interrupts. The driver doesn't
do anything but clear all interrupts at boot time, to avoid spurious
interrupts left by the firmware.
The GICP registers are directly written to in
This commit adds a simple driver for the Marvell GICP, a hardware unit
that converts memory writes into GIC SPI interrupts. The driver doesn't
do anything but clear all interrupts at boot time, to avoid spurious
interrupts left by the firmware.
The GICP registers are directly written to in
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