Re: [PATCH 4/4] clk: meson: meson8b: add the VPU clock trees

On 19/03/2019 22:51, Martin Blumenstingl wrote: > The VPU clock tree is slightly different on all three supported SoCs: > > Meson8 only has an input mux (which chooses between "fclk_div4", > "fclk_div3", "fclk_div5" and "fclk_div7"), a divider and a gate. > > Meson8b has two VPU clock trees, each

[PATCH 4/4] clk: meson: meson8b: add the VPU clock trees

The VPU clock tree is slightly different on all three supported SoCs: Meson8 only has an input mux (which chooses between "fclk_div4", "fclk_div3", "fclk_div5" and "fclk_div7"), a divider and a gate. Meson8b has two VPU clock trees, each with an input mux (using the same parents as the input mux