On 06/24/2014 07:45 PM, Marcelo Tosatti wrote:
On Sun, Jun 22, 2014 at 09:02:25PM +0200, Andi Kleen wrote:
First, it's not sufficient to pin the debug store area, you also
have to pin the guest page tables that are used to map the debug
store. But even if you do that, as soon as the guest
On 06/24/2014 07:45 PM, Marcelo Tosatti wrote:
On Sun, Jun 22, 2014 at 09:02:25PM +0200, Andi Kleen wrote:
First, it's not sufficient to pin the debug store area, you also
have to pin the guest page tables that are used to map the debug
store. But even if you do that, as soon as the guest
On Sun, Jun 22, 2014 at 09:02:25PM +0200, Andi Kleen wrote:
> > First, it's not sufficient to pin the debug store area, you also
> > have to pin the guest page tables that are used to map the debug
> > store. But even if you do that, as soon as the guest fork()s, it
> > will create a new pgd
On Sun, Jun 22, 2014 at 09:02:25PM +0200, Andi Kleen wrote:
First, it's not sufficient to pin the debug store area, you also
have to pin the guest page tables that are used to map the debug
store. But even if you do that, as soon as the guest fork()s, it
will create a new pgd which the
> First, it's not sufficient to pin the debug store area, you also
> have to pin the guest page tables that are used to map the debug
> store. But even if you do that, as soon as the guest fork()s, it
> will create a new pgd which the host will be free to swap out. The
> processor can then
On 05/30/2014 04:12 AM, Andi Kleen wrote:
From: Andi Kleen
PEBS (Precise Event Bases Sampling) profiling is very powerful,
allowing improved sampling precision and much additional information,
like address or TSX abort profiling. cycles:p and :pp uses PEBS.
This patch enables PEBS profiling
On 05/30/2014 04:12 AM, Andi Kleen wrote:
From: Andi Kleen a...@linux.intel.com
PEBS (Precise Event Bases Sampling) profiling is very powerful,
allowing improved sampling precision and much additional information,
like address or TSX abort profiling. cycles:p and :pp uses PEBS.
This patch
First, it's not sufficient to pin the debug store area, you also
have to pin the guest page tables that are used to map the debug
store. But even if you do that, as soon as the guest fork()s, it
will create a new pgd which the host will be free to swap out. The
processor can then attempt a
> > Userspace then can read/write these MSRs, and add them to the migration
> > stream. QEMU has code for that.
>
> Thanks. The PEBS setup always redoes its state, can be arbitarily often
> redone.
>
> So the only change needed would be to add the MSRs to some list in qemu?
Yes, and also
> Userspace then can read/write these MSRs, and add them to the migration
> stream. QEMU has code for that.
Thanks. The PEBS setup always redoes its state, can be arbitarily often redone.
So the only change needed would be to add the MSRs to some list in qemu?
-Andi
--
a...@linux.intel.com
Il 02/06/2014 21:57, Andi Kleen ha scritto:
> It would be a bigger concern if we expected virtual PMU migration to
> work, but I think it would be nice to update kvm_pmu_cpuid_update() to
> notice the presence/absence of the new CPUID bits, and then store that
> into per-VM kvm_pmu->pebs_allowed
Il 10/06/2014 23:06, Marcelo Tosatti ha scritto:
> BTW how about general PMU migration? As far as I can tell there
> is no code to save/restore the state for that currently, right?
Paolo wrote support for it, recently. Paolo?
Yes, on the KVM side all that is needed is to special case MSR
Il 10/06/2014 23:06, Marcelo Tosatti ha scritto:
BTW how about general PMU migration? As far as I can tell there
is no code to save/restore the state for that currently, right?
Paolo wrote support for it, recently. Paolo?
Yes, on the KVM side all that is needed is to special case MSR reads
Il 02/06/2014 21:57, Andi Kleen ha scritto:
It would be a bigger concern if we expected virtual PMU migration to
work, but I think it would be nice to update kvm_pmu_cpuid_update() to
notice the presence/absence of the new CPUID bits, and then store that
into per-VM kvm_pmu-pebs_allowed
Userspace then can read/write these MSRs, and add them to the migration
stream. QEMU has code for that.
Thanks. The PEBS setup always redoes its state, can be arbitarily often redone.
So the only change needed would be to add the MSRs to some list in qemu?
-Andi
--
a...@linux.intel.com --
Userspace then can read/write these MSRs, and add them to the migration
stream. QEMU has code for that.
Thanks. The PEBS setup always redoes its state, can be arbitarily often
redone.
So the only change needed would be to add the MSRs to some list in qemu?
Yes, and also adding them to
On Tue, Jun 10, 2014 at 12:22:07PM -0700, Andi Kleen wrote:
> On Tue, Jun 10, 2014 at 03:04:48PM -0300, Marcelo Tosatti wrote:
> > On Thu, May 29, 2014 at 06:12:07PM -0700, Andi Kleen wrote:
> > > {
> > > struct kvm_pmu *pmu = >arch.pmu;
> > > @@ -407,6 +551,20 @@ int kvm_pmu_set_msr(struct
On Tue, Jun 10, 2014 at 03:04:48PM -0300, Marcelo Tosatti wrote:
> On Thu, May 29, 2014 at 06:12:07PM -0700, Andi Kleen wrote:
> > {
> > struct kvm_pmu *pmu = >arch.pmu;
> > @@ -407,6 +551,20 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct
> > msr_data *msr_info)
> >
On Thu, May 29, 2014 at 06:12:07PM -0700, Andi Kleen wrote:
> {
> struct kvm_pmu *pmu = >arch.pmu;
> @@ -407,6 +551,20 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct
> msr_data *msr_info)
> return 0;
> }
> break;
> + case
On Thu, May 29, 2014 at 06:12:07PM -0700, Andi Kleen wrote:
{
struct kvm_pmu *pmu = vcpu-arch.pmu;
@@ -407,6 +551,20 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct
msr_data *msr_info)
return 0;
}
break;
+ case
On Tue, Jun 10, 2014 at 03:04:48PM -0300, Marcelo Tosatti wrote:
On Thu, May 29, 2014 at 06:12:07PM -0700, Andi Kleen wrote:
{
struct kvm_pmu *pmu = vcpu-arch.pmu;
@@ -407,6 +551,20 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct
msr_data *msr_info)
return
On Tue, Jun 10, 2014 at 12:22:07PM -0700, Andi Kleen wrote:
On Tue, Jun 10, 2014 at 03:04:48PM -0300, Marcelo Tosatti wrote:
On Thu, May 29, 2014 at 06:12:07PM -0700, Andi Kleen wrote:
{
struct kvm_pmu *pmu = vcpu-arch.pmu;
@@ -407,6 +551,20 @@ int kvm_pmu_set_msr(struct kvm_vcpu
> It seems to me that with this patch, there is no way to expose a
> PMU-without-PEBS to the guest if the host has PEBS.
If you clear the CPUIDs then noone would ilikely access it.
But fair enough, I'll add extra checks for CPUID.
> It would be a bigger concern if we expected virtual PMU
On Mon, Jun 02, 2014 at 07:45:35PM +0300, Gleb Natapov wrote:
> On Fri, May 30, 2014 at 09:24:24AM -0700, Andi Kleen wrote:
> > > > To avoid any problems with guest pages being swapped by the host we
> > > > pin the pages when the PEBS buffer is setup, by intercepting
> > > > that MSR.
> > > It
On Thu, May 29, 2014 at 6:12 PM, Andi Kleen wrote:
> From: Andi Kleen
>
> PEBS (Precise Event Bases Sampling) profiling is very powerful,
> allowing improved sampling precision and much additional information,
> like address or TSX abort profiling. cycles:p and :pp uses PEBS.
>
> This patch
BTW I found some more problems in the v1 version.
> > > With EPT it is less likely to happen (but still possible IIRC depending
> > > on memory
> > > pressure and how much memory shadow paging code is allowed to use),
> > > without EPT
> > > it will happen for sure.
> >
> > Don't care about
On Fri, May 30, 2014 at 09:24:24AM -0700, Andi Kleen wrote:
> > > To avoid any problems with guest pages being swapped by the host we
> > > pin the pages when the PEBS buffer is setup, by intercepting
> > > that MSR.
> > It will avoid guest page to be swapped, but shadow paging code may still
> >
On Fri, May 30, 2014 at 09:24:24AM -0700, Andi Kleen wrote:
To avoid any problems with guest pages being swapped by the host we
pin the pages when the PEBS buffer is setup, by intercepting
that MSR.
It will avoid guest page to be swapped, but shadow paging code may still
drop
BTW I found some more problems in the v1 version.
With EPT it is less likely to happen (but still possible IIRC depending
on memory
pressure and how much memory shadow paging code is allowed to use),
without EPT
it will happen for sure.
Don't care about the non EPT case,
On Thu, May 29, 2014 at 6:12 PM, Andi Kleen a...@firstfloor.org wrote:
From: Andi Kleen a...@linux.intel.com
PEBS (Precise Event Bases Sampling) profiling is very powerful,
allowing improved sampling precision and much additional information,
like address or TSX abort profiling. cycles:p and
On Mon, Jun 02, 2014 at 07:45:35PM +0300, Gleb Natapov wrote:
On Fri, May 30, 2014 at 09:24:24AM -0700, Andi Kleen wrote:
To avoid any problems with guest pages being swapped by the host we
pin the pages when the PEBS buffer is setup, by intercepting
that MSR.
It will avoid guest
It seems to me that with this patch, there is no way to expose a
PMU-without-PEBS to the guest if the host has PEBS.
If you clear the CPUIDs then noone would ilikely access it.
But fair enough, I'll add extra checks for CPUID.
It would be a bigger concern if we expected virtual PMU migration
> > To avoid any problems with guest pages being swapped by the host we
> > pin the pages when the PEBS buffer is setup, by intercepting
> > that MSR.
> It will avoid guest page to be swapped, but shadow paging code may still drop
> shadow PT pages that build a mapping from DS virtual address to
On Thu, May 29, 2014 at 06:12:07PM -0700, Andi Kleen wrote:
> From: Andi Kleen
>
> PEBS (Precise Event Bases Sampling) profiling is very powerful,
> allowing improved sampling precision and much additional information,
> like address or TSX abort profiling. cycles:p and :pp uses PEBS.
>
> This
On Thu, May 29, 2014 at 06:12:07PM -0700, Andi Kleen wrote:
From: Andi Kleen a...@linux.intel.com
PEBS (Precise Event Bases Sampling) profiling is very powerful,
allowing improved sampling precision and much additional information,
like address or TSX abort profiling. cycles:p and :pp uses
To avoid any problems with guest pages being swapped by the host we
pin the pages when the PEBS buffer is setup, by intercepting
that MSR.
It will avoid guest page to be swapped, but shadow paging code may still drop
shadow PT pages that build a mapping from DS virtual address to the guest
From: Andi Kleen
PEBS (Precise Event Bases Sampling) profiling is very powerful,
allowing improved sampling precision and much additional information,
like address or TSX abort profiling. cycles:p and :pp uses PEBS.
This patch enables PEBS profiling in KVM guests.
PEBS writes profiling records
From: Andi Kleen a...@linux.intel.com
PEBS (Precise Event Bases Sampling) profiling is very powerful,
allowing improved sampling precision and much additional information,
like address or TSX abort profiling. cycles:p and :pp uses PEBS.
This patch enables PEBS profiling in KVM guests.
PEBS
38 matches
Mail list logo
