Robert,
On Fri, Nov 16, 2012 at 08:32:24PM +0100, Robert Richter wrote:
> On 16.11.12 13:00:30, Jacob Shin wrote:
> > On Fri, Nov 16, 2012 at 07:43:44PM +0100, Robert Richter wrote:
> > > On 15.11.12 15:31:53, Jacob Shin wrote:
> > > > @@ -323,6 +368,16 @@ __amd_get_nb_event_constraints(struct
>
Robert,
On Fri, Nov 16, 2012 at 08:32:24PM +0100, Robert Richter wrote:
On 16.11.12 13:00:30, Jacob Shin wrote:
On Fri, Nov 16, 2012 at 07:43:44PM +0100, Robert Richter wrote:
On 15.11.12 15:31:53, Jacob Shin wrote:
@@ -323,6 +368,16 @@ __amd_get_nb_event_constraints(struct
Jacob,
On 16.11.12 15:57:18, Jacob Shin wrote:
> > It looks like the paths should be defined more clearly.
>
> Per comments above the function, I was logically going down the cases,
> 1. is this a legacy counter?
> 2. is this a perfctr_core counter?
> 3. is this a perfctr_nb counter?
>
> To me
Jacob,
On 16.11.12 15:57:18, Jacob Shin wrote:
It looks like the paths should be defined more clearly.
Per comments above the function, I was logically going down the cases,
1. is this a legacy counter?
2. is this a perfctr_core counter?
3. is this a perfctr_nb counter?
To me it seems
On 16.11.12 13:00:30, Jacob Shin wrote:
> > > static int setup_event_constraints(void)
> > > {
> > > - if (boot_cpu_data.x86 >= 0x15)
> > > + if (boot_cpu_data.x86 == 0x15)
> > > x86_pmu.get_event_constraints = amd_get_event_constraints_f15h;
> >
> > Since this does not cover family
On 16.11.12 13:00:30, Jacob Shin wrote:
static int setup_event_constraints(void)
{
- if (boot_cpu_data.x86 = 0x15)
+ if (boot_cpu_data.x86 == 0x15)
x86_pmu.get_event_constraints = amd_get_event_constraints_f15h;
Since this does not cover family 16h anymore, you also
On Fri, Nov 16, 2012 at 08:32:24PM +0100, Robert Richter wrote:
> On 16.11.12 13:00:30, Jacob Shin wrote:
> > On Fri, Nov 16, 2012 at 07:43:44PM +0100, Robert Richter wrote:
> > > On 15.11.12 15:31:53, Jacob Shin wrote:
> > > > @@ -156,31 +161,28 @@ static inline int amd_pmu_addr_offset(int index)
On 16.11.12 13:00:30, Jacob Shin wrote:
> On Fri, Nov 16, 2012 at 07:43:44PM +0100, Robert Richter wrote:
> > On 15.11.12 15:31:53, Jacob Shin wrote:
> > > @@ -156,31 +161,28 @@ static inline int amd_pmu_addr_offset(int index)
> > > if (offset)
> > > return offset;
> > >
> > > - if
On Fri, Nov 16, 2012 at 07:43:44PM +0100, Robert Richter wrote:
> Jacob,
>
> On 15.11.12 15:31:53, Jacob Shin wrote:
> > On AMD family 15h processors, there are 4 new performance counters
> > (in addition to 6 core performance counters) that can be used for
> > counting northbridge events (i.e.
Jacob,
On 15.11.12 15:31:53, Jacob Shin wrote:
> On AMD family 15h processors, there are 4 new performance counters
> (in addition to 6 core performance counters) that can be used for
> counting northbridge events (i.e. DRAM accesses). Their bit fields are
> almost identical to the core
Jacob,
On 15.11.12 15:31:53, Jacob Shin wrote:
On AMD family 15h processors, there are 4 new performance counters
(in addition to 6 core performance counters) that can be used for
counting northbridge events (i.e. DRAM accesses). Their bit fields are
almost identical to the core performance
On Fri, Nov 16, 2012 at 07:43:44PM +0100, Robert Richter wrote:
Jacob,
On 15.11.12 15:31:53, Jacob Shin wrote:
On AMD family 15h processors, there are 4 new performance counters
(in addition to 6 core performance counters) that can be used for
counting northbridge events (i.e. DRAM
On 16.11.12 13:00:30, Jacob Shin wrote:
On Fri, Nov 16, 2012 at 07:43:44PM +0100, Robert Richter wrote:
On 15.11.12 15:31:53, Jacob Shin wrote:
@@ -156,31 +161,28 @@ static inline int amd_pmu_addr_offset(int index)
if (offset)
return offset;
- if
On Fri, Nov 16, 2012 at 08:32:24PM +0100, Robert Richter wrote:
On 16.11.12 13:00:30, Jacob Shin wrote:
On Fri, Nov 16, 2012 at 07:43:44PM +0100, Robert Richter wrote:
On 15.11.12 15:31:53, Jacob Shin wrote:
@@ -156,31 +161,28 @@ static inline int amd_pmu_addr_offset(int index)
On AMD family 15h processors, there are 4 new performance counters
(in addition to 6 core performance counters) that can be used for
counting northbridge events (i.e. DRAM accesses). Their bit fields are
almost identical to the core performance counters. However, unlike the
core performance
On AMD family 15h processors, there are 4 new performance counters
(in addition to 6 core performance counters) that can be used for
counting northbridge events (i.e. DRAM accesses). Their bit fields are
almost identical to the core performance counters. However, unlike the
core performance
On AMD family 15h processors, there are 4 new performance counters
(in addition to 6 core performance counters) that can be used for
counting northbridge events (i.e. DRAM accesses). Their bit fields are
almost identical to the core performance counters. However, the same
set of MSRs are shared
On AMD family 15h processors, there are 4 new performance counters
(in addition to 6 core performance counters) that can be used for
counting northbridge events (i.e. DRAM accesses). Their bit fields are
almost identical to the core performance counters. However, the same
set of MSRs are shared
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