On Mon, Jan 04, 2021 at 04:30:11PM +0100, Konrad Dybcio wrote:
> Hi,
>
> could you explicitly state in the probe function (or just in the driver in
> general, as there's not much more?) and the config structs that the target
> SoC is X55?
>
The compatible says it...
> A few more SoCs
Hi,
could you explicitly state in the probe function (or just in the driver in
general, as there's not much more?) and the config structs that the target SoC
is X55?
A few more SoCs (MDM9607, MSM8x26 and some others) also use what's known as
"A7PLL" downstream, but all of them have a separate
Add support for PLL found in Qualcomm SDX55 platforms which is used to
provide clock to the Cortex A7 CPU via a mux. This PLL can provide high
frequency clock to the CPU above 1GHz as compared to the other sources
like GPLL0.
In this driver, the power domain is attached to the cpudev. This is
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