; Pawel Moll; Mark
> Rutland; Kumar Gala; Andrew Lunn; Sebastian Hesselbarth; Gregory
> Clement; linux-arm-ker...@lists.infradead.org; Nadav Haklai; Hanna Hawa;
> Yehuda Yitschak; Antoine Tenart
> Subject: [EXT] Re: [PATCH 4/6] irqchip: irq-mvebu-icu: new driver for Mar
; Pawel Moll; Mark
> Rutland; Kumar Gala; Andrew Lunn; Sebastian Hesselbarth; Gregory
> Clement; linux-arm-ker...@lists.infradead.org; Nadav Haklai; Hanna Hawa;
> Yehuda Yitschak; Antoine Tenart
> Subject: [EXT] Re: [PATCH 4/6] irqchip: irq-mvebu-icu: new driver for Mar
On Tue, May 30, 2017 at 04:49:34PM +0200, Andrew Lunn wrote:
> On Tue, May 30, 2017 at 03:39:02PM +0100, Russell King - ARM Linux wrote:
> > On Tue, May 30, 2017 at 03:27:35PM +0200, Andrew Lunn wrote:
> > > What might help is that you ask for help getting them merged. I know
> > > of at least 4
On Tue, May 30, 2017 at 04:49:34PM +0200, Andrew Lunn wrote:
> On Tue, May 30, 2017 at 03:39:02PM +0100, Russell King - ARM Linux wrote:
> > On Tue, May 30, 2017 at 03:27:35PM +0200, Andrew Lunn wrote:
> > > What might help is that you ask for help getting them merged. I know
> > > of at least 4
On Tue, May 30, 2017 at 03:39:02PM +0100, Russell King - ARM Linux wrote:
> On Tue, May 30, 2017 at 03:27:35PM +0200, Andrew Lunn wrote:
> > What might help is that you ask for help getting them merged. I know
> > of at least 4 groups of people interested in your devlink and 10G PHY
> > code. If
On Tue, May 30, 2017 at 03:39:02PM +0100, Russell King - ARM Linux wrote:
> On Tue, May 30, 2017 at 03:27:35PM +0200, Andrew Lunn wrote:
> > What might help is that you ask for help getting them merged. I know
> > of at least 4 groups of people interested in your devlink and 10G PHY
> > code. If
On Tue, May 30, 2017 at 03:27:35PM +0200, Andrew Lunn wrote:
> What might help is that you ask for help getting them merged. I know
> of at least 4 groups of people interested in your devlink and 10G PHY
> code. If you handed those patches over to these people, i'm sure we
> could find somebody to
On Tue, May 30, 2017 at 03:27:35PM +0200, Andrew Lunn wrote:
> What might help is that you ask for help getting them merged. I know
> of at least 4 groups of people interested in your devlink and 10G PHY
> code. If you handed those patches over to these people, i'm sure we
> could find somebody to
On Tue, May 30, 2017 at 04:03:20PM +0200, Andrew Lunn wrote:
> Linux has a long history of reworking stuff in tree, when it has been
> shown to be inadequate in its first version. So long as the device
> tree binding does not need incompatible changes, this reworking is not
> an issue. My guess
On Tue, May 30, 2017 at 04:03:20PM +0200, Andrew Lunn wrote:
> Linux has a long history of reworking stuff in tree, when it has been
> shown to be inadequate in its first version. So long as the device
> tree binding does not need incompatible changes, this reworking is not
> an issue. My guess
Hello,
On Tue, 30 May 2017 14:42:26 +0100, Russell King - ARM Linux wrote:
> As I've repeatedly explained - and it's called phylink, not devlink -
> the SFP support is not ready due to the SFP+ stuff needing a complete
> rewrite of that code, which has been delayed because of delays on
>
Hello,
On Tue, 30 May 2017 14:42:26 +0100, Russell King - ARM Linux wrote:
> As I've repeatedly explained - and it's called phylink, not devlink -
> the SFP support is not ready due to the SFP+ stuff needing a complete
> rewrite of that code, which has been delayed because of delays on
>
1;4601;0cOn Tue, May 30, 2017 at 02:42:26PM +0100, Russell King - ARM Linux
wrote:
> On Tue, May 30, 2017 at 03:27:35PM +0200, Andrew Lunn wrote:
> > So you don't expect to every have your 500 patches merged?
>
> Correct.
>
> > What might help is that you ask for help getting them merged. I
1;4601;0cOn Tue, May 30, 2017 at 02:42:26PM +0100, Russell King - ARM Linux
wrote:
> On Tue, May 30, 2017 at 03:27:35PM +0200, Andrew Lunn wrote:
> > So you don't expect to every have your 500 patches merged?
>
> Correct.
>
> > What might help is that you ask for help getting them merged. I
On Tue, May 30, 2017 at 03:27:35PM +0200, Andrew Lunn wrote:
> So you don't expect to every have your 500 patches merged?
Correct.
> What might help is that you ask for help getting them merged. I know
> of at least 4 groups of people interested in your devlink and 10G PHY
> code.
As I've
On Tue, May 30, 2017 at 03:27:35PM +0200, Andrew Lunn wrote:
> So you don't expect to every have your 500 patches merged?
Correct.
> What might help is that you ask for help getting them merged. I know
> of at least 4 groups of people interested in your devlink and 10G PHY
> code.
As I've
On 30/05/17 14:17, Thomas Petazzoni wrote:
> Hello,
>
> On Tue, 30 May 2017 14:06:52 +0100, Marc Zyngier wrote:
>
>>> Would drivers/irqchip/irq-mvebu-gicp.h, included by both
>>> irq-mvebu-gicp.c and irq-mvebu-icu.c be fine for you?
>>
>> Sure, that'd be fine, assuming that it is necessary
On 30/05/17 14:17, Thomas Petazzoni wrote:
> Hello,
>
> On Tue, 30 May 2017 14:06:52 +0100, Marc Zyngier wrote:
>
>>> Would drivers/irqchip/irq-mvebu-gicp.h, included by both
>>> irq-mvebu-gicp.c and irq-mvebu-icu.c be fine for you?
>>
>> Sure, that'd be fine, assuming that it is necessary
Hello,
On Tue, 30 May 2017 15:27:35 +0200, Andrew Lunn wrote:
> > Given the number of patch sets that I have, that is simply an
> > impossibility to do on a continual basis - I have close to 500
> > patches, and there's simply no way to post that number of patches.
>
> So you don't expect to
Hello,
On Tue, 30 May 2017 15:27:35 +0200, Andrew Lunn wrote:
> > Given the number of patch sets that I have, that is simply an
> > impossibility to do on a continual basis - I have close to 500
> > patches, and there's simply no way to post that number of patches.
>
> So you don't expect to
Hello,
On Tue, 30 May 2017 13:56:43 +0100, Russell King - ARM Linux wrote:
> > The problem is that you do tons of work on your side, but never submit
> > anything. Or when you submit something, it's enormous patch series that
> > hardly get reviewed because they are too big.
>
> The choice is
Hello,
On Tue, 30 May 2017 13:56:43 +0100, Russell King - ARM Linux wrote:
> > The problem is that you do tons of work on your side, but never submit
> > anything. Or when you submit something, it's enormous patch series that
> > hardly get reviewed because they are too big.
>
> The choice is
> > Once again: patches not submitted to the mailing list simply don't
> > exist. So if you continue to keep those huge stack of patches out of
> > tree and don't submit your work more regularly, in fine-grained patches
> > series, the situation we have today will continue to happen.
>
> Given
> > Once again: patches not submitted to the mailing list simply don't
> > exist. So if you continue to keep those huge stack of patches out of
> > tree and don't submit your work more regularly, in fine-grained patches
> > series, the situation we have today will continue to happen.
>
> Given
Hello,
On Tue, 30 May 2017 14:06:52 +0100, Marc Zyngier wrote:
> > Would drivers/irqchip/irq-mvebu-gicp.h, included by both
> > irq-mvebu-gicp.c and irq-mvebu-icu.c be fine for you?
>
> Sure, that'd be fine, assuming that it is necessary (see below).
Right, if we merge everything into one
Hello,
On Tue, 30 May 2017 14:06:52 +0100, Marc Zyngier wrote:
> > Would drivers/irqchip/irq-mvebu-gicp.h, included by both
> > irq-mvebu-gicp.c and irq-mvebu-icu.c be fine for you?
>
> Sure, that'd be fine, assuming that it is necessary (see below).
Right, if we merge everything into one
On 30/05/17 13:05, Thomas Petazzoni wrote:
> Hello,
>
> On Tue, 30 May 2017 12:10:29 +0100, Marc Zyngier wrote:
>
>> Thanks for that, looks pretty interesting. A couple of comments below.
>
> Thanks again for the review!
>
>>> +/* GICP registers */
>>> +#define GICP_SETSPI_NSR_OFFSET 0x0
On 30/05/17 13:05, Thomas Petazzoni wrote:
> Hello,
>
> On Tue, 30 May 2017 12:10:29 +0100, Marc Zyngier wrote:
>
>> Thanks for that, looks pretty interesting. A couple of comments below.
>
> Thanks again for the review!
>
>>> +/* GICP registers */
>>> +#define GICP_SETSPI_NSR_OFFSET 0x0
On Tue, May 30, 2017 at 02:33:50PM +0200, Thomas Petazzoni wrote:
> Hello,
>
> On Tue, 30 May 2017 13:19:07 +0100, Russell King - ARM Linux wrote:
>
> > I see we're still duplicating work.
> >
> > Yes, I know you'll reply with your "your tree is a private tree" blah
> > blah, which is fine if
On Tue, May 30, 2017 at 02:33:50PM +0200, Thomas Petazzoni wrote:
> Hello,
>
> On Tue, 30 May 2017 13:19:07 +0100, Russell King - ARM Linux wrote:
>
> > I see we're still duplicating work.
> >
> > Yes, I know you'll reply with your "your tree is a private tree" blah
> > blah, which is fine if
Hello,
On Tue, 30 May 2017 13:19:07 +0100, Russell King - ARM Linux wrote:
> I see we're still duplicating work.
>
> Yes, I know you'll reply with your "your tree is a private tree" blah
> blah, which is fine if you want to keep re-doing work that others have
> done, but it's incredibly
Hello,
On Tue, 30 May 2017 13:19:07 +0100, Russell King - ARM Linux wrote:
> I see we're still duplicating work.
>
> Yes, I know you'll reply with your "your tree is a private tree" blah
> blah, which is fine if you want to keep re-doing work that others have
> done, but it's incredibly
I see we're still duplicating work.
Yes, I know you'll reply with your "your tree is a private tree" blah
blah, which is fine if you want to keep re-doing work that others have
done, but it's incredibly inefficient.
What you call my private tree is the public ARM git tree - hardly
private. It's
I see we're still duplicating work.
Yes, I know you'll reply with your "your tree is a private tree" blah
blah, which is fine if you want to keep re-doing work that others have
done, but it's incredibly inefficient.
What you call my private tree is the public ARM git tree - hardly
private. It's
Hello,
On Tue, 30 May 2017 12:10:29 +0100, Marc Zyngier wrote:
> Thanks for that, looks pretty interesting. A couple of comments below.
Thanks again for the review!
> > +/* GICP registers */
> > +#define GICP_SETSPI_NSR_OFFSET 0x0
> > +#define GICP_CLRSPI_NSR_OFFSET 0x8
>
>
Hello,
On Tue, 30 May 2017 12:10:29 +0100, Marc Zyngier wrote:
> Thanks for that, looks pretty interesting. A couple of comments below.
Thanks again for the review!
> > +/* GICP registers */
> > +#define GICP_SETSPI_NSR_OFFSET 0x0
> > +#define GICP_CLRSPI_NSR_OFFSET 0x8
>
>
Hi Thomas,
Very small comment,
On Tue, May 30, 2017 at 11:16:09AM +0200, Thomas Petazzoni wrote:
> diff --git a/drivers/irqchip/irq-mvebu-icu.c b/drivers/irqchip/irq-mvebu-icu.c
[...]
> +#define ICU_INT_CFG(x) (0x100 + 4 * x)
You should use (x) here, to be safe.
Thanks!
Antoine
--
Hi Thomas,
Very small comment,
On Tue, May 30, 2017 at 11:16:09AM +0200, Thomas Petazzoni wrote:
> diff --git a/drivers/irqchip/irq-mvebu-icu.c b/drivers/irqchip/irq-mvebu-icu.c
[...]
> +#define ICU_INT_CFG(x) (0x100 + 4 * x)
You should use (x) here, to be safe.
Thanks!
Antoine
--
Hi Thomas,
Thanks for that, looks pretty interesting. A couple of comments below.
On 30/05/17 10:16, Thomas Petazzoni wrote:
> The Marvell ICU unit is found in the CP110 block of the Marvell Armada
> 7K and 8K SoCs. It collects the wired interrupts of the devices located
> in the CP110 and turns
Hi Thomas,
Thanks for that, looks pretty interesting. A couple of comments below.
On 30/05/17 10:16, Thomas Petazzoni wrote:
> The Marvell ICU unit is found in the CP110 block of the Marvell Armada
> 7K and 8K SoCs. It collects the wired interrupts of the devices located
> in the CP110 and turns
The Marvell ICU unit is found in the CP110 block of the Marvell Armada
7K and 8K SoCs. It collects the wired interrupts of the devices located
in the CP110 and turns them into SPI interrupts in the GIC located in
the AP806 side of the SoC, by using a memory transaction.
Until now, the ICU was
The Marvell ICU unit is found in the CP110 block of the Marvell Armada
7K and 8K SoCs. It collects the wired interrupts of the devices located
in the CP110 and turns them into SPI interrupts in the GIC located in
the AP806 side of the SoC, by using a memory transaction.
Until now, the ICU was
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