On Monday, July 20, 2015 at 11:23:39 AM, Cyrille Pitchen wrote:
> Hi Marek,
Hi!
> Le 16/07/2015 19:44, Marek Vasut a écrit :
> > On Thursday, July 16, 2015 at 05:27:51 PM, Cyrille Pitchen wrote:
> >
> > Hi!
> >
> >> Both the SPI controller and the NOR flash memory need to agree on the
> >> numb
Hi Marek,
Le 16/07/2015 19:44, Marek Vasut a écrit :
> On Thursday, July 16, 2015 at 05:27:51 PM, Cyrille Pitchen wrote:
>
> Hi!
>
>> Both the SPI controller and the NOR flash memory need to agree on the
>> number of dummy cycles to use for Fast Read commands. For Spansion
>> memories, this numb
On Thursday, July 16, 2015 at 05:27:51 PM, Cyrille Pitchen wrote:
Hi!
> Both the SPI controller and the NOR flash memory need to agree on the
> number of dummy cycles to use for Fast Read commands. For Spansion
> memories, this number of dummy cycles is not given directly but through a
> so calle
Both the SPI controller and the NOR flash memory need to agree on the
number of dummy cycles to use for Fast Read commands. For Spansion
memories, this number of dummy cycles is not given directly but through a
so called "latency code".
The latency code can be found into the memory datasheet and de
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