[PATCH 4/7] clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks

On the new Allwinner H6 SoC, multiple PLL's are NMP style clocks (modelled as NKMP with no K) and have fixed post-dividers. Add fixed post divider support to the NKMP style clocks. Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/ccu_nkmp.c | 20 +---

[PATCH 4/7] clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks

On the new Allwinner H6 SoC, multiple PLL's are NMP style clocks (modelled as NKMP with no K) and have fixed post-dividers. Add fixed post divider support to the NKMP style clocks. Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/ccu_nkmp.c | 20 +---