Re: [PATCH 4/8] phy: rockchip-usb: expose the phy-internal PLLs

2015-11-13 Thread Kishon Vijay Abraham I
Hi, On Thursday 05 November 2015 03:14 AM, Heiko Stuebner wrote: > The USB phys on Rockchip SoCs contain their own internal PLLs to create > the 480MHz needed. Additionally this PLL output is also fed back into the > core clock-controller as possible source for clocks like the GPU or others. > >

Re: [PATCH 4/8] phy: rockchip-usb: expose the phy-internal PLLs

2015-11-13 Thread Kishon Vijay Abraham I
Hi, On Thursday 05 November 2015 03:14 AM, Heiko Stuebner wrote: > The USB phys on Rockchip SoCs contain their own internal PLLs to create > the 480MHz needed. Additionally this PLL output is also fed back into the > core clock-controller as possible source for clocks like the GPU or others. > >

[PATCH 4/8] phy: rockchip-usb: expose the phy-internal PLLs

2015-11-04 Thread Heiko Stuebner
The USB phys on Rockchip SoCs contain their own internal PLLs to create the 480MHz needed. Additionally this PLL output is also fed back into the core clock-controller as possible source for clocks like the GPU or others. Until now this was modelled incorrectly with a "virtual" factor clock in

[PATCH 4/8] phy: rockchip-usb: expose the phy-internal PLLs

2015-11-04 Thread Heiko Stuebner
The USB phys on Rockchip SoCs contain their own internal PLLs to create the 480MHz needed. Additionally this PLL output is also fed back into the core clock-controller as possible source for clocks like the GPU or others. Until now this was modelled incorrectly with a "virtual" factor clock in