Re: [PATCH 4/9] clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled

2018-05-30 Thread David Lechner
On 05/30/2018 12:22 PM, Michael Turquette wrote: Quoting David Lechner (2018-05-25 11:11:45) From: Sekhar Nori PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot be disabled. Mark it so to prevent unused clock disable infrastructure from disabling it. Signed-off-by: Sekhar Nori

Re: [PATCH 4/9] clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled

2018-05-30 Thread David Lechner
On 05/30/2018 12:22 PM, Michael Turquette wrote: Quoting David Lechner (2018-05-25 11:11:45) From: Sekhar Nori PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot be disabled. Mark it so to prevent unused clock disable infrastructure from disabling it. Signed-off-by: Sekhar Nori

Re: [PATCH 4/9] clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled

2018-05-30 Thread Michael Turquette
Quoting David Lechner (2018-05-25 11:11:45) > From: Sekhar Nori > > PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot > be disabled. Mark it so to prevent unused clock disable > infrastructure from disabling it. > > Signed-off-by: Sekhar Nori > Reviewed-by: David Lechner > --- >

Re: [PATCH 4/9] clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled

2018-05-30 Thread Michael Turquette
Quoting David Lechner (2018-05-25 11:11:45) > From: Sekhar Nori > > PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot > be disabled. Mark it so to prevent unused clock disable > infrastructure from disabling it. > > Signed-off-by: Sekhar Nori > Reviewed-by: David Lechner > --- >

[PATCH 4/9] clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled

2018-05-25 Thread David Lechner
From: Sekhar Nori PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot be disabled. Mark it so to prevent unused clock disable infrastructure from disabling it. Signed-off-by: Sekhar Nori Reviewed-by: David Lechner ---

[PATCH 4/9] clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled

2018-05-25 Thread David Lechner
From: Sekhar Nori PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot be disabled. Mark it so to prevent unused clock disable infrastructure from disabling it. Signed-off-by: Sekhar Nori Reviewed-by: David Lechner --- drivers/clk/davinci/pll-dm646x.c | 2 +- 1 file changed, 1