On 05/30/2018 12:22 PM, Michael Turquette wrote:
Quoting David Lechner (2018-05-25 11:11:45)
From: Sekhar Nori
PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot
be disabled. Mark it so to prevent unused clock disable
infrastructure from disabling it.
Signed-off-by: Sekhar Nori
On 05/30/2018 12:22 PM, Michael Turquette wrote:
Quoting David Lechner (2018-05-25 11:11:45)
From: Sekhar Nori
PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot
be disabled. Mark it so to prevent unused clock disable
infrastructure from disabling it.
Signed-off-by: Sekhar Nori
Quoting David Lechner (2018-05-25 11:11:45)
> From: Sekhar Nori
>
> PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot
> be disabled. Mark it so to prevent unused clock disable
> infrastructure from disabling it.
>
> Signed-off-by: Sekhar Nori
> Reviewed-by: David Lechner
> ---
>
Quoting David Lechner (2018-05-25 11:11:45)
> From: Sekhar Nori
>
> PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot
> be disabled. Mark it so to prevent unused clock disable
> infrastructure from disabling it.
>
> Signed-off-by: Sekhar Nori
> Reviewed-by: David Lechner
> ---
>
From: Sekhar Nori
PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot
be disabled. Mark it so to prevent unused clock disable
infrastructure from disabling it.
Signed-off-by: Sekhar Nori
Reviewed-by: David Lechner
---
From: Sekhar Nori
PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot
be disabled. Mark it so to prevent unused clock disable
infrastructure from disabling it.
Signed-off-by: Sekhar Nori
Reviewed-by: David Lechner
---
drivers/clk/davinci/pll-dm646x.c | 2 +-
1 file changed, 1
6 matches
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