Re: [PATCH 5/5] perf, x86: Support Haswell v4 LBR format v2

2013-09-04 Thread Andi Kleen
On Wed, Sep 04, 2013 at 10:21:27AM -0400, Vince Weaver wrote: > On Wed, 4 Sep 2013, Andi Kleen wrote: > > > > What does this mean? The above values are exported as part of > > > include/uapi/linux/perf_event.h > > > Do they not work yet? > > > > You can filter on the fields, but you can't see

Re: [PATCH 5/5] perf, x86: Support Haswell v4 LBR format v2

2013-09-04 Thread Vince Weaver
On Wed, 4 Sep 2013, Andi Kleen wrote: > > What does this mean? The above values are exported as part of > > include/uapi/linux/perf_event.h > > Do they not work yet? > > You can filter on the fields, but you can't see them outside > the kernel driver yet. The patch to see them is still pendi

Re: [PATCH 5/5] perf, x86: Support Haswell v4 LBR format v2

2013-09-03 Thread Andi Kleen
On Tue, Sep 03, 2013 at 05:14:51PM -0400, Vince Weaver wrote: > On Tue, 3 Sep 2013, Andi Kleen wrote: > > > > > + PERF_SAMPLE_BRANCH_ABORT_TX = 1U << 7, /* transaction > > > > aborts */ > > > > + PERF_SAMPLE_BRANCH_IN_TX= 1U << 8, /* in transaction */ > > > > + PERF_

Re: [PATCH 5/5] perf, x86: Support Haswell v4 LBR format v2

2013-09-03 Thread Vince Weaver
On Tue, 3 Sep 2013, Andi Kleen wrote: > > > + PERF_SAMPLE_BRANCH_ABORT_TX = 1U << 7, /* transaction aborts */ > > > + PERF_SAMPLE_BRANCH_IN_TX= 1U << 8, /* in transaction */ > > > + PERF_SAMPLE_BRANCH_NO_TX= 1U << 9, /* not in transaction */ > > > > so if you specify these fla

Re: [PATCH 5/5] perf, x86: Support Haswell v4 LBR format v2

2013-09-03 Thread Andi Kleen
> > + PERF_SAMPLE_BRANCH_ABORT_TX = 1U << 7, /* transaction aborts */ > > + PERF_SAMPLE_BRANCH_IN_TX= 1U << 8, /* in transaction */ > > + PERF_SAMPLE_BRANCH_NO_TX= 1U << 9, /* not in transaction */ > > so if you specify these flags in branch_sample_type, what information

Re: [PATCH 5/5] perf, x86: Support Haswell v4 LBR format v2

2013-09-03 Thread Vince Weaver
On Sat, 20 Apr 2013, Andi Kleen wrote: > From: Andi Kleen > > Haswell has two additional LBR from flags for TSX: intx and abort, implemented > as a new v4 version of the LBR format. > > Handle those in and adjust the sign extension code to still correctly extend. > The flags are exported simila

[PATCH 5/5] perf, x86: Support Haswell v4 LBR format v2

2013-04-20 Thread Andi Kleen
From: Andi Kleen Haswell has two additional LBR from flags for TSX: intx and abort, implemented as a new v4 version of the LBR format. Handle those in and adjust the sign extension code to still correctly extend. The flags are exported similarly in the LBR record to the existing misprediction fl

[PATCH 5/5] perf, x86: Support Haswell v4 LBR format

2013-03-21 Thread Andi Kleen
From: Andi Kleen Haswell has two additional LBR from flags for TSX: intx and abort, implemented as a new v4 version of the LBR format. Handle those in and adjust the sign extension code to still correctly extend. The flags are exported similarly in the LBR record to the existing misprediction fl

[PATCH 5/5] perf, x86: Support Haswell v4 LBR format

2013-03-08 Thread Andi Kleen
From: Andi Kleen Haswell has two additional LBR from flags for TSX: intx and abort, implemented as a new v4 version of the LBR format. Handle those in and adjust the sign extension code to still correctly extend. The flags are exported similarly in the LBR record to the existing misprediction fl