Re: [PATCH 5/9] RISC-V: implement low-level interrupt handling

2018-08-02 Thread Christoph Hellwig
On Thu, Aug 02, 2018 at 11:48:55AM +0200, Thomas Gleixner wrote: > > diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S > > index 9aaf6c986771..fa2c08e3c05e 100644 > > --- a/arch/riscv/kernel/entry.S > > +++ b/arch/riscv/kernel/entry.S > > @@ -168,8 +168,8 @@ ENTRY(handle_exception)

Re: [PATCH 5/9] RISC-V: implement low-level interrupt handling

2018-08-02 Thread Thomas Gleixner
On Thu, 26 Jul 2018, Christoph Hellwig wrote: > Add support for a routine that dispatches exceptions with the interrupt > flags set to either the IPI or irqdomain code (and the clock source in the > future). > > Loosely based on the irq-riscv-int.c irqchip driver from the RISC-V tree. > > Signed-

[PATCH 5/9] RISC-V: implement low-level interrupt handling

2018-07-26 Thread Christoph Hellwig
Add support for a routine that dispatches exceptions with the interrupt flags set to either the IPI or irqdomain code (and the clock source in the future). Loosely based on the irq-riscv-int.c irqchip driver from the RISC-V tree. Signed-off-by: Christoph Hellwig --- arch/riscv/kernel/entry.S |