Re: [PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size

2016-08-23 Thread Suzuki K Poulose
On 22/08/16 11:00, Will Deacon wrote: On Thu, Aug 18, 2016 at 02:10:30PM +0100, Suzuki K Poulose wrote: On systems with mismatched i/d cache min line sizes, we need to use the smallest size possible across all CPUs. This will be done by fetching the system wide safe value from CPU feature

Re: [PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size

2016-08-23 Thread Suzuki K Poulose
On 22/08/16 11:00, Will Deacon wrote: On Thu, Aug 18, 2016 at 02:10:30PM +0100, Suzuki K Poulose wrote: On systems with mismatched i/d cache min line sizes, we need to use the smallest size possible across all CPUs. This will be done by fetching the system wide safe value from CPU feature

Re: [PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size

2016-08-22 Thread Will Deacon
On Thu, Aug 18, 2016 at 02:10:30PM +0100, Suzuki K Poulose wrote: > On systems with mismatched i/d cache min line sizes, we need to use > the smallest size possible across all CPUs. This will be done by fetching > the system wide safe value from CPU feature infrastructure. > However the some

Re: [PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size

2016-08-22 Thread Will Deacon
On Thu, Aug 18, 2016 at 02:10:30PM +0100, Suzuki K Poulose wrote: > On systems with mismatched i/d cache min line sizes, we need to use > the smallest size possible across all CPUs. This will be done by fetching > the system wide safe value from CPU feature infrastructure. > However the some

Re: [PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size

2016-08-18 Thread Geoff Levand
On Thu, 2016-08-18 at 14:10 +0100, Suzuki K Poulose wrote: > On systems with mismatched i/d cache min line sizes, we need to use > the smallest size possible across all CPUs. This will be done by fetching > the system wide safe value from CPU feature infrastructure. > However the some special

Re: [PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size

2016-08-18 Thread Geoff Levand
On Thu, 2016-08-18 at 14:10 +0100, Suzuki K Poulose wrote: > On systems with mismatched i/d cache min line sizes, we need to use > the smallest size possible across all CPUs. This will be done by fetching > the system wide safe value from CPU feature infrastructure. > However the some special

[PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size

2016-08-18 Thread Suzuki K Poulose
On systems with mismatched i/d cache min line sizes, we need to use the smallest size possible across all CPUs. This will be done by fetching the system wide safe value from CPU feature infrastructure. However the some special users(e.g kexec, hibernate) would need the line size on the CPU (rather

[PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size

2016-08-18 Thread Suzuki K Poulose
On systems with mismatched i/d cache min line sizes, we need to use the smallest size possible across all CPUs. This will be done by fetching the system wide safe value from CPU feature infrastructure. However the some special users(e.g kexec, hibernate) would need the line size on the CPU (rather

Re: [PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size

2016-08-09 Thread James Morse
Hi Suzuki, Sorry this fell through the cracks... On 08/07/16 12:37, Suzuki K Poulose wrote: > On systems with mismatched i/d cache min line sizes, we need to use > the smallest size possible across all CPUs. This will be done by fetching > the system wide safe value from CPU feature

Re: [PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size

2016-08-09 Thread James Morse
Hi Suzuki, Sorry this fell through the cracks... On 08/07/16 12:37, Suzuki K Poulose wrote: > On systems with mismatched i/d cache min line sizes, we need to use > the smallest size possible across all CPUs. This will be done by fetching > the system wide safe value from CPU feature

Re: [PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size

2016-07-11 Thread Geoff Levand
On Fri, 2016-07-08 at 12:37 +0100, Suzuki K Poulose wrote: > On systems with mismatched i/d cache min line sizes, we need to use > the smallest size possible across all CPUs. This will be done by fetching > the system wide safe value from CPU feature infrastructure. > However the some special

Re: [PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size

2016-07-11 Thread Geoff Levand
On Fri, 2016-07-08 at 12:37 +0100, Suzuki K Poulose wrote: > On systems with mismatched i/d cache min line sizes, we need to use > the smallest size possible across all CPUs. This will be done by fetching > the system wide safe value from CPU feature infrastructure. > However the some special

[PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size

2016-07-08 Thread Suzuki K Poulose
On systems with mismatched i/d cache min line sizes, we need to use the smallest size possible across all CPUs. This will be done by fetching the system wide safe value from CPU feature infrastructure. However the some special users(e.g kexec, hibernate) would need the line size on the CPU (rather

[PATCH 6/8] arm64: Introduce raw_{d,i}cache_line_size

2016-07-08 Thread Suzuki K Poulose
On systems with mismatched i/d cache min line sizes, we need to use the smallest size possible across all CPUs. This will be done by fetching the system wide safe value from CPU feature infrastructure. However the some special users(e.g kexec, hibernate) would need the line size on the CPU (rather