Re: [PATCH 6/8] clk: tegra30: add 2d and 3d idle clocks

2018-07-24 Thread Ben Dooks
On 24/07/18 12:31, Dmitry Osipenko wrote: On Monday, 23 July 2018 16:05:21 MSK Dmitry Osipenko wrote: On Friday, 20 July 2018 16:45:30 MSK Ben Dooks wrote: The 2D and 3D clocks have an IDLE field in bits 15:8 so add these clocks by making a 2D and 3D mux, and split the divider into the standard

Re: [PATCH 6/8] clk: tegra30: add 2d and 3d idle clocks

2018-07-24 Thread Dmitry Osipenko
On Monday, 23 July 2018 16:05:21 MSK Dmitry Osipenko wrote: > On Friday, 20 July 2018 16:45:30 MSK Ben Dooks wrote: > > The 2D and 3D clocks have an IDLE field in bits 15:8 so add these > > clocks by making a 2D and 3D mux, and split the divider into the > > standard 2D/3D ones and 2D/3D idle clock

Re: [PATCH 6/8] clk: tegra30: add 2d and 3d idle clocks

2018-07-23 Thread Dmitry Osipenko
On Friday, 20 July 2018 16:45:30 MSK Ben Dooks wrote: > The 2D and 3D clocks have an IDLE field in bits 15:8 so add these > clocks by making a 2D and 3D mux, and split the divider into the > standard 2D/3D ones and 2D/3D idle clocks. > > Signed-off-by: Ben Dooks > --- > drivers/clk/tegra/clk-id.

Re: [PATCH 6/8] clk: tegra30: add 2d and 3d idle clocks

2018-07-23 Thread Ben Dooks
On 2018-07-23 12:33, Dmitry Osipenko wrote: On Monday, 23 July 2018 11:28:25 MSK Ben Dooks wrote: On 2018-07-22 12:55, Dmitry Osipenko wrote: > On Friday, 20 July 2018 16:45:30 MSK Ben Dooks wrote: >> The 2D and 3D clocks have an IDLE field in bits 15:8 so add these >> clocks by making a 2D a

Re: [PATCH 6/8] clk: tegra30: add 2d and 3d idle clocks

2018-07-23 Thread Dmitry Osipenko
On Monday, 23 July 2018 11:28:25 MSK Ben Dooks wrote: > On 2018-07-22 12:55, Dmitry Osipenko wrote: > > On Friday, 20 July 2018 16:45:30 MSK Ben Dooks wrote: > >> The 2D and 3D clocks have an IDLE field in bits 15:8 so add these > >> clocks by making a 2D and 3D mux, and split the divider into the

Re: [PATCH 6/8] clk: tegra30: add 2d and 3d idle clocks

2018-07-23 Thread Ben Dooks
On 2018-07-22 12:55, Dmitry Osipenko wrote: On Friday, 20 July 2018 16:45:30 MSK Ben Dooks wrote: The 2D and 3D clocks have an IDLE field in bits 15:8 so add these clocks by making a 2D and 3D mux, and split the divider into the standard 2D/3D ones and 2D/3D idle clocks. Signed-off-by: Ben D

Re: [PATCH 6/8] clk: tegra30: add 2d and 3d idle clocks

2018-07-22 Thread Dmitry Osipenko
On Friday, 20 July 2018 16:45:30 MSK Ben Dooks wrote: > The 2D and 3D clocks have an IDLE field in bits 15:8 so add these > clocks by making a 2D and 3D mux, and split the divider into the > standard 2D/3D ones and 2D/3D idle clocks. > > Signed-off-by: Ben Dooks > --- > drivers/clk/tegra/clk-id.

[PATCH 6/8] clk: tegra30: add 2d and 3d idle clocks

2018-07-20 Thread Ben Dooks
The 2D and 3D clocks have an IDLE field in bits 15:8 so add these clocks by making a 2D and 3D mux, and split the divider into the standard 2D/3D ones and 2D/3D idle clocks. Signed-off-by: Ben Dooks --- drivers/clk/tegra/clk-id.h | 4 drivers/clk/tegra/clk-tegra-periph.c|