On 2/6/2021 3:09 AM, Namhyung Kim wrote:
On Fri, Feb 5, 2021 at 11:38 PM Liang, Kan wrote:
On 2/5/2021 6:08 AM, Namhyung Kim wrote:
On Wed, Feb 3, 2021 at 5:14 AM wrote:
From: Kan Liang
The instruction latency information can be recorded on some platforms,
e.g., the Intel Sapphire Rap
> On 05-Feb-2021, at 8:21 PM, Liang, Kan wrote:
>
>
>
> On 2/5/2021 7:55 AM, Athira Rajeev wrote:
Because in other archs, the var2_w of ‘perf_sample_weight’ could be used
to capture something else than the Local INSTR Latency.
Can we have some weak function to populate the he
On Fri, Feb 5, 2021 at 11:38 PM Liang, Kan wrote:
>
> On 2/5/2021 6:08 AM, Namhyung Kim wrote:
> > On Wed, Feb 3, 2021 at 5:14 AM wrote:
> >>
> >> From: Kan Liang
> >>
> >> The instruction latency information can be recorded on some platforms,
> >> e.g., the Intel Sapphire Rapids server. With bo
> On 04-Feb-2021, at 8:49 PM, Liang, Kan wrote:
>
>
>
> On 2/4/2021 8:11 AM, Athira Rajeev wrote:
>>> On 03-Feb-2021, at 1:39 AM, kan.li...@linux.intel.com wrote:
>>>
>>> From: Kan Liang
>>>
>>> The instruction latency information can be recorded on some platforms,
>>> e.g., the Intel Sap
On 2/5/2021 7:55 AM, Athira Rajeev wrote:
Because in other archs, the var2_w of ‘perf_sample_weight’ could be used to
capture something else than the Local INSTR Latency.
Can we have some weak function to populate the header string ?
I agree that the var2_w has different meanings among archi
On 2/5/2021 6:08 AM, Namhyung Kim wrote:
On Wed, Feb 3, 2021 at 5:14 AM wrote:
From: Kan Liang
The instruction latency information can be recorded on some platforms,
e.g., the Intel Sapphire Rapids server. With both memory latency
(weight) and the new instruction latency information, user
On Wed, Feb 3, 2021 at 5:14 AM wrote:
>
> From: Kan Liang
>
> The instruction latency information can be recorded on some platforms,
> e.g., the Intel Sapphire Rapids server. With both memory latency
> (weight) and the new instruction latency information, users can easily
> locate the expensive l
On 2/4/2021 8:11 AM, Athira Rajeev wrote:
On 03-Feb-2021, at 1:39 AM, kan.li...@linux.intel.com wrote:
From: Kan Liang
The instruction latency information can be recorded on some platforms,
e.g., the Intel Sapphire Rapids server. With both memory latency
(weight) and the new instruction
> On 03-Feb-2021, at 1:39 AM, kan.li...@linux.intel.com wrote:
>
> From: Kan Liang
>
> The instruction latency information can be recorded on some platforms,
> e.g., the Intel Sapphire Rapids server. With both memory latency
> (weight) and the new instruction latency information, users can ea
Em Tue, Feb 02, 2021 at 12:09:10PM -0800, kan.li...@linux.intel.com escreveu:
> From: Kan Liang
>
> The instruction latency information can be recorded on some platforms,
> e.g., the Intel Sapphire Rapids server. With both memory latency
> (weight) and the new instruction latency information, use
From: Kan Liang
The instruction latency information can be recorded on some platforms,
e.g., the Intel Sapphire Rapids server. With both memory latency
(weight) and the new instruction latency information, users can easily
locate the expensive load instructions, and also understand the time
spent
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