Re: [PATCH 7/9] powerpc/powernv: Add platform support for stop instruction

2016-05-03 Thread Shreyas B Prabhu
On 05/03/2016 10:55 AM, Michael Neuling wrote: > >> diff --git a/arch/powerpc/include/asm/cputable.h >> b/arch/powerpc/include/asm/cputable.h >> index df4fb5f..a4739a1 100644 >> --- a/arch/powerpc/include/asm/cputable.h >> +++ b/arch/powerpc/include/asm/cputable.h >> @@ -205,6 +205,7 @@ enum {

Re: [PATCH 7/9] powerpc/powernv: Add platform support for stop instruction

2016-05-03 Thread Shreyas B Prabhu
On 05/03/2016 10:55 AM, Michael Neuling wrote: > >> diff --git a/arch/powerpc/include/asm/cputable.h >> b/arch/powerpc/include/asm/cputable.h >> index df4fb5f..a4739a1 100644 >> --- a/arch/powerpc/include/asm/cputable.h >> +++ b/arch/powerpc/include/asm/cputable.h >> @@ -205,6 +205,7 @@ enum {

Re: [PATCH 7/9] powerpc/powernv: Add platform support for stop instruction

2016-05-02 Thread Michael Neuling
> diff --git a/arch/powerpc/include/asm/cputable.h > b/arch/powerpc/include/asm/cputable.h > index df4fb5f..a4739a1 100644 > --- a/arch/powerpc/include/asm/cputable.h > +++ b/arch/powerpc/include/asm/cputable.h > @@ -205,6 +205,7 @@ enum { >  #define CPU_FTR_DABRX >

Re: [PATCH 7/9] powerpc/powernv: Add platform support for stop instruction

2016-05-02 Thread Michael Neuling
> diff --git a/arch/powerpc/include/asm/cputable.h > b/arch/powerpc/include/asm/cputable.h > index df4fb5f..a4739a1 100644 > --- a/arch/powerpc/include/asm/cputable.h > +++ b/arch/powerpc/include/asm/cputable.h > @@ -205,6 +205,7 @@ enum { >  #define CPU_FTR_DABRX >

[PATCH 7/9] powerpc/powernv: Add platform support for stop instruction

2016-04-21 Thread Shreyas B. Prabhu
POWER ISA v3 defines a new idle processor core mechanism. In summary, a) new instruction named stop is added. This instruction replaces instructions like nap, sleep, rvwinkle. b) new per thread SPR named PSSCR is added which controls the behavior of stop instruction. PSSCR has

[PATCH 7/9] powerpc/powernv: Add platform support for stop instruction

2016-04-21 Thread Shreyas B. Prabhu
POWER ISA v3 defines a new idle processor core mechanism. In summary, a) new instruction named stop is added. This instruction replaces instructions like nap, sleep, rvwinkle. b) new per thread SPR named PSSCR is added which controls the behavior of stop instruction. PSSCR has