On Wed, Apr 1, 2015 at 6:14 PM, Linus Torvalds
wrote:
> On Wed, Apr 1, 2015 at 1:52 PM, Denys Vlasenko wrote:
>>
>> BTW, AMD64 docs do explicitly say that MOVs from segment registers
>> to gpregs are zero-extending.
>
> Yeah, I think anything even *remotely* recent enough to do 64-bit does
> zero
On Wed, Apr 1, 2015 at 1:52 PM, Denys Vlasenko wrote:
>
> BTW, AMD64 docs do explicitly say that MOVs from segment registers
> to gpregs are zero-extending.
Yeah, I think anything even *remotely* recent enough to do 64-bit does
zero-extending.
Even on the 32-bit side, anything that does register
On 04/01/2015 01:52 PM, Denys Vlasenko wrote:
> On 04/01/2015 05:50 PM, Linus Torvalds wrote:
>> On Wed, Apr 1, 2015 at 4:10 AM, Denys Vlasenko wrote:
>>>
>>> I did not know that. I was sure they are always zero extended.
>>
>> On all half-way modern cpu's they are. But on some older cpu's
>> (pos
On 04/01/2015 05:50 PM, Linus Torvalds wrote:
> On Wed, Apr 1, 2015 at 4:10 AM, Denys Vlasenko wrote:
>>
>> I did not know that. I was sure they are always zero extended.
>
> On all half-way modern cpu's they are. But on some older cpu's
> (possibly just the original 386) the segment move instruc
On Wed, Apr 1, 2015 at 4:10 AM, Denys Vlasenko wrote:
>
> I did not know that. I was sure they are always zero extended.
On all half-way modern cpu's they are. But on some older cpu's
(possibly just the original 386) the segment move instructions
basically are always 16-bit, and the operand size
On 04/01/2015 12:21 AM, Brian Gerst wrote:
> On Tue, Mar 31, 2015 at 1:00 PM, Denys Vlasenko wrote:
>> After TESTs, use logically correct JZ mnemonic instead of JE
>> (this doesn't change code).
>>
>> Tidy up CMPW insns:
>>
>> Modern CPUs are not good with 16-bit operations.
>> The instructions wi
* Denys Vlasenko wrote:
> After TESTs, use logically correct JZ mnemonic instead of JE
> (this doesn't change code).
>
> Tidy up CMPW insns:
>
> Modern CPUs are not good with 16-bit operations.
> The instructions with 16-bit immediates are especially bad,
> on many CPUs they cause length chang
On Tue, Mar 31, 2015 at 3:21 PM, Brian Gerst wrote:
>>
>> @@ -708,7 +708,7 @@ END(sysenter_badsys)
>> #ifdef CONFIG_X86_ESPFIX32
>> movl %ss, %eax
>> /* see if on espfix stack */
>> - cmpw $__ESPFIX_SS, %ax
>> + cmpl $__ESPFIX_SS, %eax
>> jne 27f
>> mov
On Tue, Mar 31, 2015 at 1:00 PM, Denys Vlasenko wrote:
> After TESTs, use logically correct JZ mnemonic instead of JE
> (this doesn't change code).
>
> Tidy up CMPW insns:
>
> Modern CPUs are not good with 16-bit operations.
> The instructions with 16-bit immediates are especially bad,
> on many C
After TESTs, use logically correct JZ mnemonic instead of JE
(this doesn't change code).
Tidy up CMPW insns:
Modern CPUs are not good with 16-bit operations.
The instructions with 16-bit immediates are especially bad,
on many CPUs they cause length changing prefix stall
in the decoders, costing ~
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