On Thu, 31 Jan 2019 12:40:04 +
wrote:
> On 01/31/2019 01:55 PM, Boris Brezillon wrote:
> > On Wed, 30 Jan 2019 15:08:47 +
> > wrote:
> >
> >> +
> >> +static int atmel_sam9x60_qspi_set_cfg(struct atmel_qspi *aq,
> >> +const struct spi_mem_op *op,
> >> +
On 01/31/2019 01:55 PM, Boris Brezillon wrote:
> On Wed, 30 Jan 2019 15:08:47 +
> wrote:
>
>> +
>> +static int atmel_sam9x60_qspi_set_cfg(struct atmel_qspi *aq,
>> + const struct spi_mem_op *op,
>> + struct atmel_qspi_cfg
On Wed, 30 Jan 2019 15:08:47 +
wrote:
> +/*
> + * atmel_qspi_set_address_mode() - set address mode.
> + * @cfg: contains register values
> + * @op: describes a SPI memory operation
> + *
> + * The controller allows 24 and 32-bit addressing while NAND-flash requires
> + *
On Wed, 30 Jan 2019 15:08:47 +
wrote:
> +
> +static int atmel_sam9x60_qspi_set_cfg(struct atmel_qspi *aq,
> + const struct spi_mem_op *op,
> + struct atmel_qspi_cfg *cfg)
> +{
> + int ret = atmel_qspi_set_mode(cfg, op);
On 01/30/2019 07:43 PM, Boris Brezillon wrote:
> On Wed, 30 Jan 2019 15:08:47 +
> wrote:
>
>> +static int atmel_sam9x60_qspi_clk_prepare_enable(struct atmel_qspi *aq)
>> +{
>> +struct device *dev = >pdev->dev;
>> +int ret;
>> +
>> +if (!aq->clk) {
>> +/* Get the
On Wed, 30 Jan 2019 15:08:47 +
wrote:
> +static int atmel_sam9x60_qspi_clk_prepare_enable(struct atmel_qspi *aq)
> +{
> + struct device *dev = >pdev->dev;
> + int ret;
> +
> + if (!aq->clk) {
> + /* Get the peripheral clock */
> + aq->clk =
From: Tudor Ambarus
The sam9x60 qspi controller uses 2 clocks, one for the peripheral register
access, the other for the qspi core and phy. Both are mandatory. It uses
dedicated register for Read Instruction Code Register (RICR) and
Write Instruction Code Register (WICR). ICR/RICR/WICR have
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