On Sun, Sep 29, 2019 at 07:40:28PM +0200, Martin Blumenstingl wrote:
Hi Sasha,
On Sun, Sep 29, 2019 at 7:34 PM Sasha Levin wrote:
From: Martin Blumenstingl
[ Upstream commit ed90302be64a53d9031c8ce05428c358b16a5d96 ]
The mainline PCIe PHY driver has it's own devicetree node. Update the
clo
Hi Sasha,
On Sun, Sep 29, 2019 at 7:34 PM Sasha Levin wrote:
>
> From: Martin Blumenstingl
>
> [ Upstream commit ed90302be64a53d9031c8ce05428c358b16a5d96 ]
>
> The mainline PCIe PHY driver has it's own devicetree node. Update the
> clock alias so the mainline driver finds the clocks.
the mainlin
From: Martin Blumenstingl
[ Upstream commit ed90302be64a53d9031c8ce05428c358b16a5d96 ]
The mainline PCIe PHY driver has it's own devicetree node. Update the
clock alias so the mainline driver finds the clocks.
The first PCIe PHY is located at 0x1f106800 and exists on VRX200, ARX300
and GRX390.
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