Re: [PATCH AUTOSEL 5.3 087/203] ASoC: mediatek: mt6358: add delay after dmic clock on

2019-10-01 Thread Sasha Levin
On Mon, Sep 23, 2019 at 11:21:59AM -0700, Mark Brown wrote: On Sun, Sep 22, 2019 at 02:41:53PM -0400, Sasha Levin wrote: From: Jiaxin Yu [ Upstream commit ccb1fa21ef58a2ac15519bb878470762e967e8b3 ] Most dmics produce a high level when they receive clock. The difference between power-on and me

Re: [PATCH AUTOSEL 5.3 087/203] ASoC: mediatek: mt6358: add delay after dmic clock on

2019-09-23 Thread Mark Brown
On Sun, Sep 22, 2019 at 02:41:53PM -0400, Sasha Levin wrote: > From: Jiaxin Yu > > [ Upstream commit ccb1fa21ef58a2ac15519bb878470762e967e8b3 ] > > Most dmics produce a high level when they receive clock. The difference > between power-on and memory record time is about 10ms, but the dmic > need

[PATCH AUTOSEL 5.3 087/203] ASoC: mediatek: mt6358: add delay after dmic clock on

2019-09-22 Thread Sasha Levin
From: Jiaxin Yu [ Upstream commit ccb1fa21ef58a2ac15519bb878470762e967e8b3 ] Most dmics produce a high level when they receive clock. The difference between power-on and memory record time is about 10ms, but the dmic needs 50ms to output normal data. This commit add 100ms delay after SoC output