[PATCH AUTOSEL 5.4 14/38] drm/amd/powerplay: correct Vega20 cached smu feature state

[Sasha Levin]

From: Evan Quan <evan.q...@amd.com>

[ Upstream commit 266d81d9eed30f4994d76a2b237c63ece062eefe ]

Correct the cached smu feature state on pp_features sysfs
setting.

Signed-off-by: Evan Quan <evan.q...@amd.com>
Acked-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Sasha Levin <sas...@kernel.org>
---
 .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c    | 38 +++++++++----------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c 
b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index f5915308e643a..08b91c31532ba 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -981,27 +981,15 @@ static int vega20_disable_all_smu_features(struct 
pp_hwmgr *hwmgr)
 {
        struct vega20_hwmgr *data =
                        (struct vega20_hwmgr *)(hwmgr->backend);
-       uint64_t features_enabled;
-       int i;
-       bool enabled;
-       int ret = 0;
+       int i, ret = 0;
 
        PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr,
                        PPSMC_MSG_DisableAllSmuFeatures)) == 0,
                        "[DisableAllSMUFeatures] Failed to disable all smu 
features!",
                        return ret);
 
-       ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
-       PP_ASSERT_WITH_CODE(!ret,
-                       "[DisableAllSMUFeatures] Failed to get enabled smc 
features!",
-                       return ret);
-
-       for (i = 0; i < GNLD_FEATURES_MAX; i++) {
-               enabled = (features_enabled & 
data->smu_features[i].smu_feature_bitmap) ?
-                       true : false;
-               data->smu_features[i].enabled = enabled;
-               data->smu_features[i].supported = enabled;
-       }
+       for (i = 0; i < GNLD_FEATURES_MAX; i++)
+               data->smu_features[i].enabled = 0;
 
        return 0;
 }
@@ -3211,10 +3199,11 @@ static int vega20_get_ppfeature_status(struct pp_hwmgr 
*hwmgr, char *buf)
 
 static int vega20_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t 
new_ppfeature_masks)
 {
-       uint64_t features_enabled;
-       uint64_t features_to_enable;
-       uint64_t features_to_disable;
-       int ret = 0;
+       struct vega20_hwmgr *data =
+                       (struct vega20_hwmgr *)(hwmgr->backend);
+       uint64_t features_enabled, features_to_enable, features_to_disable;
+       int i, ret = 0;
+       bool enabled;
 
        if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
                return -EINVAL;
@@ -3243,6 +3232,17 @@ static int vega20_set_ppfeature_status(struct pp_hwmgr 
*hwmgr, uint64_t new_ppfe
                        return ret;
        }
 
+       /* Update the cached feature enablement state */
+       ret = vega20_get_enabled_smc_features(hwmgr, &features_enabled);
+       if (ret)
+               return ret;
+
+       for (i = 0; i < GNLD_FEATURES_MAX; i++) {
+               enabled = (features_enabled & 
data->smu_features[i].smu_feature_bitmap) ?
+                       true : false;
+               data->smu_features[i].enabled = enabled;
+       }
+
        return 0;
 }
 
-- 
2.25.1