[PATCH AUTOSEL 5.7 48/54] drm/amdkfd: fix the wrong sdma instance query for renoir

[Sasha Levin]

From: Huang Rui <ray.hu...@amd.com>

[ Upstream commit 34174b89bfa495bed9cddcc504fb38feca90fab7 ]

Renoir only has one sdma instance, it will get failed once query the
sdma1 registers. So use switch-case instead of static register array.

Signed-off-by: Huang Rui <ray.hu...@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehl...@amd.com>
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
Signed-off-by: Sasha Levin <sas...@kernel.org>
---
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 31 +++++++++++++------
 1 file changed, 22 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
index df841c2ac5e74..cdcf3b8e914a7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
@@ -197,19 +197,32 @@ static uint32_t get_sdma_rlc_reg_offset(struct 
amdgpu_device *adev,
                                unsigned int engine_id,
                                unsigned int queue_id)
 {
-       uint32_t sdma_engine_reg_base[2] = {
-               SOC15_REG_OFFSET(SDMA0, 0,
-                                mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL,
-               SOC15_REG_OFFSET(SDMA1, 0,
-                                mmSDMA1_RLC0_RB_CNTL) - mmSDMA1_RLC0_RB_CNTL
-       };
-       uint32_t retval = sdma_engine_reg_base[engine_id]
+       uint32_t sdma_engine_reg_base = 0;
+       uint32_t sdma_rlc_reg_offset;
+
+       switch (engine_id) {
+       default:
+               dev_warn(adev->dev,
+                        "Invalid sdma engine id (%d), using engine id 0\n",
+                        engine_id);
+               fallthrough;
+       case 0:
+               sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0,
+                               mmSDMA0_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
+               break;
+       case 1:
+               sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA1, 0,
+                               mmSDMA1_RLC0_RB_CNTL) - mmSDMA0_RLC0_RB_CNTL;
+               break;
+       }
+
+       sdma_rlc_reg_offset = sdma_engine_reg_base
                + queue_id * (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL);
 
        pr_debug("RLC register offset for SDMA%d RLC%d: 0x%x\n", engine_id,
-                       queue_id, retval);
+                queue_id, sdma_rlc_reg_offset);
 
-       return retval;
+       return sdma_rlc_reg_offset;
 }
 
 static inline struct v9_mqd *get_mqd(void *mqd)
-- 
2.25.1