Add DSB after icache flush to complete the cache maintenance operation.
Signed-off-by: Vinayak Kale
Acked-by: Catalin Marinas
Cc:
---
KernelVersion: 3.14-rc1
PS:
- This patch is tested for ARM-v7.
arch/arm/include/asm/cacheflush.h |1 +
1 file changed, 1 insertion(+)
diff --git
On Tue, Feb 11, 2014 at 09:10:11AM +, Vinayak Kale wrote:
> Add DSB after icache flush to complete the cache maintenance operation.
>
> Signed-off-by: Vinayak Kale
> Acked-by: Catalin Marinas
I guess what you need to do is add:
Cc:
and send the patch to Russell's patch system (and add
Add DSB after icache flush to complete the cache maintenance operation.
Signed-off-by: Vinayak Kale
Acked-by: Catalin Marinas
---
PS:
- This patch is tested for ARM-v7.
arch/arm/include/asm/cacheflush.h |1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/cacheflush.h
Add DSB after icache flush to complete the cache maintenance operation.
Signed-off-by: Vinayak Kale vk...@apm.com
Acked-by: Catalin Marinas catalin.mari...@arm.com
---
PS:
- This patch is tested for ARM-v7.
arch/arm/include/asm/cacheflush.h |1 +
1 file changed, 1 insertion(+)
diff --git
On Tue, Feb 11, 2014 at 09:10:11AM +, Vinayak Kale wrote:
Add DSB after icache flush to complete the cache maintenance operation.
Signed-off-by: Vinayak Kale vk...@apm.com
Acked-by: Catalin Marinas catalin.mari...@arm.com
I guess what you need to do is add:
Cc: sta...@vger.kernel.org
Add DSB after icache flush to complete the cache maintenance operation.
Signed-off-by: Vinayak Kale vk...@apm.com
Acked-by: Catalin Marinas catalin.mari...@arm.com
Cc: sta...@vger.kernel.org
---
KernelVersion: 3.14-rc1
PS:
- This patch is tested for ARM-v7.
arch/arm/include/asm/cacheflush.h |
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