Hi,
On 07-05-16 07:30, Chen-Yu Tsai wrote:
Hi,
On Tue, Apr 12, 2016 at 9:38 AM, Chen-Yu Tsai wrote:
On Tue, Apr 12, 2016 at 3:23 AM, Florian Fainelli wrote:
On 04/04/16 09:22, Chen-Yu Tsai wrote:
The Allwinner H3 SoC incorporates an Ethernet PHY. This is enabled and
configured through a me
Hi,
On Tue, Apr 12, 2016 at 9:38 AM, Chen-Yu Tsai wrote:
> On Tue, Apr 12, 2016 at 3:23 AM, Florian Fainelli
> wrote:
>> On 04/04/16 09:22, Chen-Yu Tsai wrote:
>>> The Allwinner H3 SoC incorporates an Ethernet PHY. This is enabled and
>>> configured through a memory mapped hardware register.
>>
On Tue, Apr 12, 2016 at 3:23 AM, Florian Fainelli wrote:
> On 04/04/16 09:22, Chen-Yu Tsai wrote:
>> The Allwinner H3 SoC incorporates an Ethernet PHY. This is enabled and
>> configured through a memory mapped hardware register.
>>
>> This same register also configures the MAC interface mode and T
On 04/04/16 09:22, Chen-Yu Tsai wrote:
> The Allwinner H3 SoC incorporates an Ethernet PHY. This is enabled and
> configured through a memory mapped hardware register.
>
> This same register also configures the MAC interface mode and TX clock
> source. Also covered by the register, but not support
On Tue, Apr 05, 2016 at 12:22:30AM +0800, Chen-Yu Tsai wrote:
> The Allwinner H3 SoC incorporates an Ethernet PHY. This is enabled and
> configured through a memory mapped hardware register.
>
> This same register also configures the MAC interface mode and TX clock
> source. Also covered by the re
The Allwinner H3 SoC incorporates an Ethernet PHY. This is enabled and
configured through a memory mapped hardware register.
This same register also configures the MAC interface mode and TX clock
source. Also covered by the register, but not supported in these bindings,
are TX/RX clock delay chain
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