Re: [PATCH RFC 3/4] KVM: MMU: Add 5 level EPT & Shadow page table support.

2017-03-09 Thread Paolo Bonzini
On 29/12/2016 10:26, Liang Li wrote: > The future Intel CPU will extend the max physical address to 52 bits. > To support the new physical address width, EPT is extended to support > 5 level page table. > This patch add the 5 level EPT and extend shadow page to support > 5 level paging guest. As

[PATCH RFC 3/4] KVM: MMU: Add 5 level EPT & Shadow page table support.

2016-12-29 Thread Liang Li
The future Intel CPU will extend the max physical address to 52 bits. To support the new physical address width, EPT is extended to support 5 level page table. This patch add the 5 level EPT and extend shadow page to support 5 level paging guest. As the RFC version, this patch enables 5 level EPT o