On Mon, Aug 05, 2019 at 10:24:42PM +0530, Vidya Sagar wrote:
[...]
> > > > IRQs are enabled when you call a suspend_noirq() callback, so the
> > > > blocking API can be used as long as the IRQ descriptor backing
> > > > the IRQ that will wake-up the blocked call is marked as
> > > > IRQF_NO_SUSPE
On 8/5/2019 7:31 PM, Lorenzo Pieralisi wrote:
On Fri, Aug 02, 2019 at 05:36:43PM +0530, Vidya Sagar wrote:
On 7/30/2019 9:19 PM, Lorenzo Pieralisi wrote:
On Tue, Jul 23, 2019 at 08:14:08PM +0530, Vidya Sagar wrote:
On 7/16/2019 4:52 PM, Lorenzo Pieralisi wrote:
On Sat, Jul 13, 2019 at 12:34:3
On Fri, Aug 02, 2019 at 05:36:43PM +0530, Vidya Sagar wrote:
> On 7/30/2019 9:19 PM, Lorenzo Pieralisi wrote:
> > On Tue, Jul 23, 2019 at 08:14:08PM +0530, Vidya Sagar wrote:
> > > On 7/16/2019 4:52 PM, Lorenzo Pieralisi wrote:
> > > > On Sat, Jul 13, 2019 at 12:34:34PM +0530, Vidya Sagar wrote:
>
On 7/30/2019 9:19 PM, Lorenzo Pieralisi wrote:
On Tue, Jul 23, 2019 at 08:14:08PM +0530, Vidya Sagar wrote:
On 7/16/2019 4:52 PM, Lorenzo Pieralisi wrote:
On Sat, Jul 13, 2019 at 12:34:34PM +0530, Vidya Sagar wrote:
[...]
+static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
On Tue, Jul 23, 2019 at 08:14:08PM +0530, Vidya Sagar wrote:
> On 7/16/2019 4:52 PM, Lorenzo Pieralisi wrote:
> > On Sat, Jul 13, 2019 at 12:34:34PM +0530, Vidya Sagar wrote:
> >
> > [...]
> >
> > > > > > > +static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw
> > > > > > > *pcie,
> >
On 7/16/2019 4:52 PM, Lorenzo Pieralisi wrote:
On Sat, Jul 13, 2019 at 12:34:34PM +0530, Vidya Sagar wrote:
[...]
+static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
+ bool enable)
+{
+ struct mrq_uphy_response resp;
+ stru
Maddireddy ;
sagar...@gmail.com
Subject: Re: [PATCH V13 12/12] PCI: tegra: Add Tegra194 PCIe support
On Tue, Jul 16, 2019 at 12:22:25PM +0100, Lorenzo Pieralisi wrote:
> On Sat, Jul 13, 2019 at 12:34:34PM +0530, Vidya Sagar wrote:
> > > > > So if the link is not up we still go ah
On Tue, Jul 16, 2019 at 12:22:25PM +0100, Lorenzo Pieralisi wrote:
> On Sat, Jul 13, 2019 at 12:34:34PM +0530, Vidya Sagar wrote:
> > > > > So if the link is not up we still go ahead and make probe
> > > > > succeed. What for ?
> > > > We may need root port to be available to support hot-plugging
On Sat, Jul 13, 2019 at 12:34:34PM +0530, Vidya Sagar wrote:
[...]
> > > > > +static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
> > > > > + bool enable)
> > > > > +{
> > > > > + struct mrq_uphy_response resp;
> > > > > + struct teg
On 7/12/2019 9:37 PM, Lorenzo Pieralisi wrote:
On Fri, Jul 12, 2019 at 09:02:49PM +0530, Vidya Sagar wrote:
[...]
+static irqreturn_t tegra_pcie_irq_handler(int irq, void *arg)
+{
+ struct tegra_pcie_dw *pcie = arg;
+
+ if (pcie->mode == DW_PCIE_RC_TYPE)
+ return tegr
On Fri, Jul 12, 2019 at 09:02:49PM +0530, Vidya Sagar wrote:
[...]
> > > +static irqreturn_t tegra_pcie_irq_handler(int irq, void *arg)
> > > +{
> > > + struct tegra_pcie_dw *pcie = arg;
> > > +
> > > + if (pcie->mode == DW_PCIE_RC_TYPE)
> > > + return tegra_pcie_rp_irq_handler(pcie);
> >
On 7/11/2019 6:24 PM, Lorenzo Pieralisi wrote:
On Wed, Jul 10, 2019 at 11:52:12AM +0530, Vidya Sagar wrote:
[...]
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c
b/drivers/pci/controller/dwc/pcie-tegra194.c
new file mode 100644
index ..189779edd976
--- /dev/null
+++ b/driv
On Wed, Jul 10, 2019 at 11:52:12AM +0530, Vidya Sagar wrote:
[...]
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c
> b/drivers/pci/controller/dwc/pcie-tegra194.c
> new file mode 100644
> index ..189779edd976
> --- /dev/null
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
On 7/10/2019 10:32 PM, Lorenzo Pieralisi wrote:
On Wed, Jul 10, 2019 at 11:52:12AM +0530, Vidya Sagar wrote:
[...]
+#if defined(CONFIG_PCIEASPM)
+static void disable_aspm_l11(struct tegra_pcie_dw *pcie)
+{
+ u32 val;
+
+ val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub)
On Wed, Jul 10, 2019 at 11:52:12AM +0530, Vidya Sagar wrote:
[...]
> +#if defined(CONFIG_PCIEASPM)
> +static void disable_aspm_l11(struct tegra_pcie_dw *pcie)
> +{
> + u32 val;
> +
> + val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
> + val &= ~PCI_L1SS_CAP_ASPM_L1_1;
>
Add support for Synopsys DesignWare core IP based PCIe host controller
present in Tegra194 SoC.
Signed-off-by: Vidya Sagar
Acked-by: Thierry Reding
---
V13:
* Modified according to modifications in PATCH V13 01/12
V12:
* None
V11:
* None
V10:
* Used _relaxed() versions of readl() & writel()
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