On 8/13/2019 4:27 PM, Lorenzo Pieralisi wrote:
Some style comments - we have time to fix them.
On Fri, Aug 09, 2019 at 10:16:09AM +0530, Vidya Sagar wrote:
[...]
I do not know why up to here the line spacing is OK and here
you started cramming code all together :)
Just a matter of consistency
Some style comments - we have time to fix them.
On Fri, Aug 09, 2019 at 10:16:09AM +0530, Vidya Sagar wrote:
[...]
I do not know why up to here the line spacing is OK and here
you started cramming code all together :)
Just a matter of consistency, thanks for fixing them up.
> +static void tegr
Add support for Synopsys DesignWare core IP based PCIe host controller
present in Tegra194 SoC.
Signed-off-by: Vidya Sagar
Acked-by: Thierry Reding
---
V15:
* Refactored the code to use only tegra_bpmp_transfer() API in .probe()
as well as .resume_noirq() path.
This is made possible by http:
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