[PATCH V19 2/7] i2c: tegra: add bus clear Master Support

2019-02-12 Thread Sowjanya Komatineni
Bus clear feature of Tegra I2C controller helps to recover from bus hang when I2C master loses the bus arbitration due to the slave device holding SDA LOW continuously for some unknown reasons. Per I2C specification, the device that held the bus LOW should release it within 9 clock pulses.

[PATCH V19 2/7] i2c: tegra: add bus clear Master Support

2019-02-12 Thread Sowjanya Komatineni
Bus clear feature of Tegra I2C controller helps to recover from bus hang when I2C master loses the bus arbitration due to the slave device holding SDA LOW continuously for some unknown reasons. Per I2C specification, the device that held the bus LOW should release it within 9 clock pulses.

[PATCH V19 2/7] i2c: tegra: add bus clear Master Support

2019-02-12 Thread Sowjanya Komatineni
Bus clear feature of Tegra I2C controller helps to recover from bus hang when I2C master loses the bus arbitration due to the slave device holding SDA LOW continuously for some unknown reasons. Per I2C specification, the device that held the bus LOW should release it within 9 clock pulses.