Re: [PATCH V2] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

2018-06-01 Thread David E. Box
On Wed, 2018-05-30 at 17:03 +0530, Rajneesh Bhardwaj wrote: > On Wed, May 30, 2018 at 03:53:12AM -0700, David E. Box wrote: > > Hi Dave, > > > Hi Rajneesh, > > > > On Mon, 2018-05-28 at 12:30 +0530, Rajneesh Bhardwaj wrote: > > > On Thu, May 24, 2018 at 06:10:56PM -0700, David E. Box wrote: > >

Re: [PATCH V2] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

2018-06-01 Thread Andy Shevchenko
On Fri, Jun 1, 2018 at 2:04 AM, David E. Box wrote: > On Thu, 2018-05-31 at 21:38 +0300, Andy Shevchenko wrote: >> On Fri, May 25, 2018 at 4:10 AM, David E. Box >> wrote: >> > +struct slps0_dbg_map { >> > + const struct pmc_bit_map *slps0_dbg_sts; >> > + int size; >> > +}; >> >> Didn

Re: [PATCH V2] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

2018-05-31 Thread David E. Box
On Thu, 2018-05-31 at 21:38 +0300, Andy Shevchenko wrote: > On Fri, May 25, 2018 at 4:10 AM, David E. Box > wrote: > > Adds debugfs access to registers in the Cannon Point PCH PMC that > > are > > useful for debugging #SLP_S0 signal assertion and other low power > > related > > activities. Device

Re: [PATCH V2] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

2018-05-31 Thread Andy Shevchenko
On Fri, May 25, 2018 at 4:10 AM, David E. Box wrote: > Adds debugfs access to registers in the Cannon Point PCH PMC that are > useful for debugging #SLP_S0 signal assertion and other low power related > activities. Device pm states are latched in these registers whenever the > package enters C10 a

Re: [PATCH V2] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

2018-05-30 Thread Rajneesh Bhardwaj
On Wed, May 30, 2018 at 03:53:12AM -0700, David E. Box wrote: Hi Dave, > Hi Rajneesh, > > On Mon, 2018-05-28 at 12:30 +0530, Rajneesh Bhardwaj wrote: > > On Thu, May 24, 2018 at 06:10:56PM -0700, David E. Box wrote: > > > > Thanks for sending this, Dave. Few comments below. > > > > > Adds debu

Re: [PATCH V2] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

2018-05-30 Thread David E. Box
Hi Rajneesh, On Mon, 2018-05-28 at 12:30 +0530, Rajneesh Bhardwaj wrote: > On Thu, May 24, 2018 at 06:10:56PM -0700, David E. Box wrote: > > Thanks for sending this, Dave. Few comments below. > > > Adds debugfs access to registers in the Cannon Point PCH PMC that > > are > > Please use Cannonla

Re: [PATCH V2] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

2018-05-28 Thread Rajneesh Bhardwaj
On Thu, May 24, 2018 at 06:10:56PM -0700, David E. Box wrote: Thanks for sending this, Dave. Few comments below. > Adds debugfs access to registers in the Cannon Point PCH PMC that are Please use Cannonlake PCH. > useful for debugging #SLP_S0 signal assertion and other low power related assert

[PATCH V2] platform/x86: intel_pmc_core: Add CNP SLPS0 debug registers

2018-05-24 Thread David E. Box
Adds debugfs access to registers in the Cannon Point PCH PMC that are useful for debugging #SLP_S0 signal assertion and other low power related activities. Device pm states are latched in these registers whenever the package enters C10 and can be read from slp_s0_debug_status. The pm states may als