Re: [PATCH V2 06/19] csky: Cache and TLB routines

On Thu, Jul 05, 2018 at 07:40:25PM +0200, Peter Zijlstra wrote: > > +#ifdef CONFIG_SMP > > +#define mb() asm volatile ("sync.is":::"memory") > > +#else > > +#define mb() asm volatile ("sync":::"memory") > > +#endif > > This is very suspect, please elaborate. > > What I would've

Re: [PATCH V2 06/19] csky: Cache and TLB routines

On Thu, Jul 05, 2018 at 07:40:25PM +0200, Peter Zijlstra wrote: > > +#ifdef CONFIG_SMP > > +#define mb() asm volatile ("sync.is":::"memory") > > +#else > > +#define mb() asm volatile ("sync":::"memory") > > +#endif > > This is very suspect, please elaborate. > > What I would've

Re: [PATCH V2 06/19] csky: Cache and TLB routines

On Mon, Jul 02, 2018 at 01:30:09AM +0800, Guo Ren wrote: > diff --git a/arch/csky/include/asm/barrier.h b/arch/csky/include/asm/barrier.h > new file mode 100644 > index 000..7254527 > --- /dev/null > +++ b/arch/csky/include/asm/barrier.h > @@ -0,0 +1,19 @@ > +// SPDX-License-Identifier:

Re: [PATCH V2 06/19] csky: Cache and TLB routines

On Mon, Jul 02, 2018 at 01:30:09AM +0800, Guo Ren wrote: > diff --git a/arch/csky/include/asm/barrier.h b/arch/csky/include/asm/barrier.h > new file mode 100644 > index 000..7254527 > --- /dev/null > +++ b/arch/csky/include/asm/barrier.h > @@ -0,0 +1,19 @@ > +// SPDX-License-Identifier:

[PATCH V2 06/19] csky: Cache and TLB routines

Signed-off-by: Guo Ren --- arch/csky/abiv1/cacheflush.c | 51 + arch/csky/abiv1/inc/abi/cacheflush.h | 42 +++ arch/csky/abiv1/inc/abi/tlb.h | 11 ++ arch/csky/abiv2/cacheflush.c | 55 + arch/csky/abiv2/inc/abi/cacheflush.h | 38 ++

[PATCH V2 06/19] csky: Cache and TLB routines

Signed-off-by: Guo Ren --- arch/csky/abiv1/cacheflush.c | 51 + arch/csky/abiv1/inc/abi/cacheflush.h | 42 +++ arch/csky/abiv1/inc/abi/tlb.h | 11 ++ arch/csky/abiv2/cacheflush.c | 55 + arch/csky/abiv2/inc/abi/cacheflush.h | 38 ++