[PATCH V2 1/5] spi: s3c64xx: modified error interrupt handling and init

The status of the interrupt is available in the status register, so reading the clear pending register and writing back the same value will not actually clear the pending interrupts. This patch modifies the interrupt handler to read the status register and clear the corresponding pending bit in

[PATCH V2 1/5] spi: s3c64xx: modified error interrupt handling and init

The status of the interrupt is available in the status register, so reading the clear pending register and writing back the same value will not actually clear the pending interrupts. This patch modifies the interrupt handler to read the status register and clear the corresponding pending bit in