On 4/11/2019 9:33 AM, Peter Zijlstra wrote:
On Thu, Apr 11, 2019 at 09:30:10AM -0400, Liang, Kan wrote:
I changed that like so:
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3508,7 +3508,7 @@ tnt_get_event_constraints(struct cpu_hw_
*/
if
On Thu, Apr 11, 2019 at 09:30:10AM -0400, Liang, Kan wrote:
> > I changed that like so:
> >
> > --- a/arch/x86/events/intel/core.c
> > +++ b/arch/x86/events/intel/core.c
> > @@ -3508,7 +3508,7 @@ tnt_get_event_constraints(struct cpu_hw_
> > */
> > if (event->attr.precise_ip == 3) {
> >
On 4/11/2019 5:06 AM, Peter Zijlstra wrote:
On Wed, Apr 10, 2019 at 11:57:09AM -0700, kan.li...@linux.intel.com wrote:
+static struct event_constraint *
+tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
+ struct perf_event *event)
That 'tnt' still
On Wed, Apr 10, 2019 at 11:57:09AM -0700, kan.li...@linux.intel.com wrote:
> +static struct event_constraint *
> +tnt_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
> + struct perf_event *event)
That 'tnt' still cracks me up, I keep seeing explosions.
> +{
> +
From: Kan Liang
Add perf core PMU support for Intel Tremont CPU.
The init code is based on Goldmont plus.
The generic purpose counter 0 and fixed counter 0 have less skid.
Force :ppp events on generic purpose counter 0.
Force instruction:ppp on generic purpose counter 0 and fixed counter 0.
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