> If you want a uarch name, that might be the name of the core
> ( something-cove ... I can't keep track of the names of all the
GoldenCove for Sapphire Rapids/AlderLake.
But keep in mind that they're still different. Kind of like a different
distro with different patches and configuration fr
On Thu, Mar 11, 2021 at 09:09:57PM +, Luck, Tony wrote:
> >> I think the "sapphire_rapids" is the code name for the server platform.
> >
> > If that's really the case, then:
> >
> > #define INTEL_FAM6_SAPPHIRERAPIDS_X 0x8F
> >
> > is wrong, those things should be uarch name, not platform na
>> I think the "sapphire_rapids" is the code name for the server platform.
>
> If that's really the case, then:
>
> #define INTEL_FAM6_SAPPHIRERAPIDS_X 0x8F
>
> is wrong, those things should be uarch name, not platform name. Tony?
0x8F is the model number of the CPU that is named Sapphire Rapi
On Thu, Mar 11, 2021 at 03:32:44PM -0500, Liang, Kan wrote:
> I think the "sapphire_rapids" is the code name for the server platform.
If that's really the case, then:
#define INTEL_FAM6_SAPPHIRERAPIDS_X 0x8F
is wrong, those things should be uarch name, not platform name. Tony?
On Thu, Mar 11, 2021 at 12:30:53PM -0800, Andi Kleen wrote:
> But what would you do with the information that the core is related
> to some other core.
Reduce mental clutter I suppose... there are simply too many variations
of all this about :-(
> In the end you need to know that Alderlake is Al
On 3/11/2021 2:58 PM, Peter Zijlstra wrote:
On Thu, Mar 11, 2021 at 11:53:35AM -0500, Liang, Kan wrote:
The "cpu_core" PMU is similar to the Sapphire Rapids PMU, but without
PMEM.
The "cpu_atom" PMU is similar to Tremont, but with different
event_constraints, extra_regs and number of counter
On Thu, Mar 11, 2021 at 08:58:32PM +0100, Peter Zijlstra wrote:
> On Thu, Mar 11, 2021 at 11:53:35AM -0500, Liang, Kan wrote:
>
> > > > The "cpu_core" PMU is similar to the Sapphire Rapids PMU, but without
> > > > PMEM.
> > > > The "cpu_atom" PMU is similar to Tremont, but with different
> > > > e
On Thu, Mar 11, 2021 at 11:53:35AM -0500, Liang, Kan wrote:
> > > The "cpu_core" PMU is similar to the Sapphire Rapids PMU, but without
> > > PMEM.
> > > The "cpu_atom" PMU is similar to Tremont, but with different
> > > event_constraints, extra_regs and number of counters.
> > So do these things
On 3/11/2021 11:32 AM, Peter Zijlstra wrote:
On Thu, Mar 11, 2021 at 05:09:25PM +0100, Peter Zijlstra wrote:
On Wed, Mar 10, 2021 at 08:37:56AM -0800, kan.li...@linux.intel.com wrote:
From: Kan Liang
Alder Lake Hybrid system has two different types of core, Golden Cove
core and Gracemont c
On 3/11/2021 11:53 AM, Liang, Kan wrote:
On 3/11/2021 11:09 AM, Peter Zijlstra wrote:
On Wed, Mar 10, 2021 at 08:37:56AM -0800, kan.li...@linux.intel.com
wrote:
From: Kan Liang
Alder Lake Hybrid system has two different types of core, Golden Cove
core and Gracemont core. The Golden Cove
On 3/11/2021 11:09 AM, Peter Zijlstra wrote:
On Wed, Mar 10, 2021 at 08:37:56AM -0800, kan.li...@linux.intel.com wrote:
From: Kan Liang
Alder Lake Hybrid system has two different types of core, Golden Cove
core and Gracemont core. The Golden Cove core is registered to
"cpu_core" PMU. The Gr
On Thu, Mar 11, 2021 at 05:09:25PM +0100, Peter Zijlstra wrote:
> On Wed, Mar 10, 2021 at 08:37:56AM -0800, kan.li...@linux.intel.com wrote:
> > From: Kan Liang
> >
> > Alder Lake Hybrid system has two different types of core, Golden Cove
> > core and Gracemont core. The Golden Cove core is regis
On Wed, Mar 10, 2021 at 08:37:56AM -0800, kan.li...@linux.intel.com wrote:
> From: Kan Liang
>
> Alder Lake Hybrid system has two different types of core, Golden Cove
> core and Gracemont core. The Golden Cove core is registered to
> "cpu_core" PMU. The Gracemont core is registered to "cpu_atom"
On Wed, Mar 10, 2021 at 08:37:56AM -0800, kan.li...@linux.intel.com wrote:
> @@ -4059,6 +4099,34 @@ tfa_get_event_constraints(struct cpu_hw_events *cpuc,
> int idx,
> return c;
> }
>
> +static struct event_constraint *
> +adl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
> +
From: Kan Liang
Alder Lake Hybrid system has two different types of core, Golden Cove
core and Gracemont core. The Golden Cove core is registered to
"cpu_core" PMU. The Gracemont core is registered to "cpu_atom" PMU.
The difference between the two PMUs include:
- Number of GP and fixed counters
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