Hi Juergen,
Can you rebase the patchset to 3.18.0-rc1? There are some minor merge
conflicts.
Thanks,
-Toshi
On Fri, 2014-10-24 at 06:08 +0200, Juergen Gross wrote:
> Ping?
>
> On 10/20/2014 05:59 AM, Juergen Gross wrote:
> > Hi x86 maintainers,
> >
> > any reason you seem to ignore this patch
Ping?
On 10/20/2014 05:59 AM, Juergen Gross wrote:
Hi x86 maintainers,
any reason you seem to ignore this patch series? I think I've replied
to all open issues and sent the patches more than one month ago. Each
patch has a "Reviewed-by". Is there something else missing?
Juergen
On 10/13/2014
Hi x86 maintainers,
any reason you seem to ignore this patch series? I think I've replied
to all open issues and sent the patches more than one month ago. Each
patch has a "Reviewed-by". Is there something else missing?
Juergen
On 10/13/2014 10:13 AM, Juergen Gross wrote:
The x86 architecture
The x86 architecture offers via the PAT (Page Attribute Table) a way to
specify different caching modes in page table entries. The PAT MSR contains
8 entries each specifying one of 6 possible cache modes. A pte references one
of those entries via 3 bits: _PAGE_PAT, _PAGE_PWT and _PAGE_PCD.
The Lin
Hi,
any chance to have this in 3.18?
Juergen
On 09/12/2014 12:35 PM, Juergen Gross wrote:
The x86 architecture offers via the PAT (Page Attribute Table) a way to
specify different caching modes in page table entries. The PAT MSR contains
8 entries each specifying one of 6 possible cache modes.
The x86 architecture offers via the PAT (Page Attribute Table) a way to
specify different caching modes in page table entries. The PAT MSR contains
8 entries each specifying one of 6 possible cache modes. A pte references one
of those entries via 3 bits: _PAGE_PAT, _PAGE_PWT and _PAGE_PCD.
The Lin
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