Re: [PATCH V3 0/4] megachips-stdpxxxx-ge-b850v3-fw

2017-03-08 Thread Lucas Stach
Am Mittwoch, den 08.03.2017, 10:42 +0100 schrieb Peter Senna Tschudin: > On Mon, Mar 06, 2017 at 03:27:16PM +0530, Archit Taneja wrote: > Hi Archit, > > > Hi, > > > > On 3/3/2017 9:27 PM, Peter Senna Tschudin wrote: > > > The video processing pipeline on the second output on the GE B850v3: > > >

Re: [PATCH V3 0/4] megachips-stdpxxxx-ge-b850v3-fw

2017-03-08 Thread Lucas Stach
Am Mittwoch, den 08.03.2017, 10:42 +0100 schrieb Peter Senna Tschudin: > On Mon, Mar 06, 2017 at 03:27:16PM +0530, Archit Taneja wrote: > Hi Archit, > > > Hi, > > > > On 3/3/2017 9:27 PM, Peter Senna Tschudin wrote: > > > The video processing pipeline on the second output on the GE B850v3: > > >

Re: [PATCH V3 0/4] megachips-stdpxxxx-ge-b850v3-fw

2017-03-08 Thread Peter Senna Tschudin
On Mon, Mar 06, 2017 at 03:27:16PM +0530, Archit Taneja wrote: Hi Archit, > Hi, > > On 3/3/2017 9:27 PM, Peter Senna Tschudin wrote: > > The video processing pipeline on the second output on the GE B850v3: > > > > Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output > > >

Re: [PATCH V3 0/4] megachips-stdpxxxx-ge-b850v3-fw

2017-03-08 Thread Peter Senna Tschudin
On Mon, Mar 06, 2017 at 03:27:16PM +0530, Archit Taneja wrote: Hi Archit, > Hi, > > On 3/3/2017 9:27 PM, Peter Senna Tschudin wrote: > > The video processing pipeline on the second output on the GE B850v3: > > > > Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output > > >

Re: [PATCH V3 0/4] megachips-stdpxxxx-ge-b850v3-fw

2017-03-06 Thread Archit Taneja
Hi, On 3/3/2017 9:27 PM, Peter Senna Tschudin wrote: The video processing pipeline on the second output on the GE B850v3: Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output Each bridge has a dedicated flash containing firmware for supporting the custom design. The

Re: [PATCH V3 0/4] megachips-stdpxxxx-ge-b850v3-fw

2017-03-06 Thread Archit Taneja
Hi, On 3/3/2017 9:27 PM, Peter Senna Tschudin wrote: The video processing pipeline on the second output on the GE B850v3: Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output Each bridge has a dedicated flash containing firmware for supporting the custom design. The

[PATCH V3 0/4] megachips-stdpxxxx-ge-b850v3-fw

2017-03-03 Thread Peter Senna Tschudin
The video processing pipeline on the second output on the GE B850v3: Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output Each bridge has a dedicated flash containing firmware for supporting the custom design. The result is that in this design neither the STDP4028 nor the

[PATCH V3 0/4] megachips-stdpxxxx-ge-b850v3-fw

2017-03-03 Thread Peter Senna Tschudin
The video processing pipeline on the second output on the GE B850v3: Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output Each bridge has a dedicated flash containing firmware for supporting the custom design. The result is that in this design neither the STDP4028 nor the