Am Mittwoch, den 08.03.2017, 10:42 +0100 schrieb Peter Senna Tschudin:
> On Mon, Mar 06, 2017 at 03:27:16PM +0530, Archit Taneja wrote:
> Hi Archit,
>
> > Hi,
> >
> > On 3/3/2017 9:27 PM, Peter Senna Tschudin wrote:
> > > The video processing pipeline on the second output on the GE B850v3:
> > >
On Mon, Mar 06, 2017 at 03:27:16PM +0530, Archit Taneja wrote:
Hi Archit,
> Hi,
>
> On 3/3/2017 9:27 PM, Peter Senna Tschudin wrote:
> > The video processing pipeline on the second output on the GE B850v3:
> >
> > Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output
> >
>
Hi,
On 3/3/2017 9:27 PM, Peter Senna Tschudin wrote:
The video processing pipeline on the second output on the GE B850v3:
Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output
Each bridge has a dedicated flash containing firmware for supporting the
custom design. The resul
The video processing pipeline on the second output on the GE B850v3:
Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output
Each bridge has a dedicated flash containing firmware for supporting the
custom design. The result is that in this design neither the STDP4028
nor the ST
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