On 3/26/2019 9:47 AM, Thomas Gleixner wrote:
On Tue, 26 Mar 2019, Liang, Kan wrote:
On 3/25/2019 8:11 PM, Thomas Gleixner wrote:
-#define REG_RESERVED (~((1ULL << PERF_REG_X86_MAX) - 1ULL))
+#define REG_RESERVED 0
What's the point of having this around?
I once thought it may be kept
On Tue, 26 Mar 2019, Liang, Kan wrote:
> On 3/25/2019 8:11 PM, Thomas Gleixner wrote:
>
> -#define REG_RESERVED (~((1ULL << PERF_REG_X86_MAX) - 1ULL))
> +#define REG_RESERVED 0
What's the point of having this around?
> int perf_reg_validate(u64 mask)
> {
> if (!mask || mask &
On 3/25/2019 8:11 PM, Thomas Gleixner wrote:
On Fri, 22 Mar 2019, kan.li...@linux.intel.com wrote:
+ PERF_REG_X86_XMM15 = 62,
+
+ /* All registers include the XMMX registers */
+ PERF_REG_X86_MAX = PERF_REG_X86_XMM15 + 2,
Ergo: PERF_REG_X86_MAX == 64
-#define
On Fri, 22 Mar 2019, kan.li...@linux.intel.com wrote:
>
> + PERF_REG_X86_XMM15 = 62,
> +
> + /* All registers include the XMMX registers */
> + PERF_REG_X86_MAX = PERF_REG_X86_XMM15 + 2,
Ergo: PERF_REG_X86_MAX == 64
> -#define REG_RESERVED (~((1ULL << PERF_REG_X86_MAX) - 1ULL))
>
On Mon, 25 Mar 2019, Liang, Kan wrote:
> On 3/23/2019 5:56 AM, Peter Zijlstra wrote:
> > On Fri, Mar 22, 2019 at 10:22:50AM -0700, Andi Kleen wrote:
> > > > > diff --git a/arch/x86/include/uapi/asm/perf_regs.h
> > > > > b/arch/x86/include/uapi/asm/perf_regs.h
> > > > > index
On 3/23/2019 5:56 AM, Peter Zijlstra wrote:
On Fri, Mar 22, 2019 at 10:22:50AM -0700, Andi Kleen wrote:
diff --git a/arch/x86/include/uapi/asm/perf_regs.h
b/arch/x86/include/uapi/asm/perf_regs.h
index f3329cabce5c..b33995313d17 100644
--- a/arch/x86/include/uapi/asm/perf_regs.h
+++
On Fri, Mar 22, 2019 at 10:22:50AM -0700, Andi Kleen wrote:
> > > diff --git a/arch/x86/include/uapi/asm/perf_regs.h
> > > b/arch/x86/include/uapi/asm/perf_regs.h
> > > index f3329cabce5c..b33995313d17 100644
> > > --- a/arch/x86/include/uapi/asm/perf_regs.h
> > > +++
> > diff --git a/arch/x86/include/uapi/asm/perf_regs.h
> > b/arch/x86/include/uapi/asm/perf_regs.h
> > index f3329cabce5c..b33995313d17 100644
> > --- a/arch/x86/include/uapi/asm/perf_regs.h
> > +++ b/arch/x86/include/uapi/asm/perf_regs.h
> > @@ -28,7 +28,29 @@ enum perf_event_x86_regs {
> >
On Fri, Mar 22, 2019 at 09:36:56AM -0700, kan.li...@linux.intel.com wrote:
> From: Kan Liang
>
> Starting from Icelake, XMM registers can be collected in PEBS record.
> But current code only output the pt_regs.
>
> Add a new struct x86_perf_regs for both pt_regs and xmm_regs.
> XMM registers
From: Kan Liang
Starting from Icelake, XMM registers can be collected in PEBS record.
But current code only output the pt_regs.
Add a new struct x86_perf_regs for both pt_regs and xmm_regs.
XMM registers are 128 bit. To simplify the code, they are handled like
two different registers, which
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