Re: [PATCH V3 2/6] clk: tegra: add TEGRA30_CLK_NOR to init table

2016-11-03 Thread Jon Hunter
On 27/10/16 15:01, Mirza Krak wrote: From: Mirza Krak Add TEGRA30_CLK_NOR to init table and set default rate to 127 MHz which is max rate. The maximum rate value of 127 MHz is pulled from the downstream L4T kernel. Signed-off-by: Mirza Krak Tested-by: Marcel Ziswiler Tested-on: Colibri T20

[PATCH V3 2/6] clk: tegra: add TEGRA30_CLK_NOR to init table

2016-10-27 Thread Mirza Krak
From: Mirza Krak Add TEGRA30_CLK_NOR to init table and set default rate to 127 MHz which is max rate. The maximum rate value of 127 MHz is pulled from the downstream L4T kernel. Signed-off-by: Mirza Krak Tested-by: Marcel Ziswiler Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Bo