On 2017-03-23 11:33, Mark Rutland wrote:
Hi Agustin,
Structurally, this looks good to me.
I have a few minor comments below; with those fixed up I think this is
ready to merge.
Thanks Mark, I'll spin V5 ASAP.
Agustin
--
Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm
On 2017-03-23 11:33, Mark Rutland wrote:
Hi Agustin,
Structurally, this looks good to me.
I have a few minor comments below; with those fixed up I think this is
ready to merge.
Thanks Mark, I'll spin V5 ASAP.
Agustin
--
Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm
Hi Agustin,
Structurally, this looks good to me.
I have a few minor comments below; with those fixed up I think this is
ready to merge.
On Fri, Mar 17, 2017 at 10:24:17AM -0400, Agustin Vega-Frias wrote:
> +/*
> + * General constants
> + */
> +
> +/* Number of counters on each PMU */
> +#define
Hi Agustin,
Structurally, this looks good to me.
I have a few minor comments below; with those fixed up I think this is
ready to merge.
On Fri, Mar 17, 2017 at 10:24:17AM -0400, Agustin Vega-Frias wrote:
> +/*
> + * General constants
> + */
> +
> +/* Number of counters on each PMU */
> +#define
On 2017-03-17 10:24, Agustin Vega-Frias wrote:
This adds a new dynamic PMU to the Perf Events framework to program
and control the L3 cache PMUs in some Qualcomm Technologies SOCs.
The driver supports a distributed cache architecture where the overall
cache for a socket is comprised of multiple
On 2017-03-17 10:24, Agustin Vega-Frias wrote:
This adds a new dynamic PMU to the Perf Events framework to program
and control the L3 cache PMUs in some Qualcomm Technologies SOCs.
The driver supports a distributed cache architecture where the overall
cache for a socket is comprised of multiple
This adds a new dynamic PMU to the Perf Events framework to program
and control the L3 cache PMUs in some Qualcomm Technologies SOCs.
The driver supports a distributed cache architecture where the overall
cache for a socket is comprised of multiple slices each with its own PMU.
Access to each
This adds a new dynamic PMU to the Perf Events framework to program
and control the L3 cache PMUs in some Qualcomm Technologies SOCs.
The driver supports a distributed cache architecture where the overall
cache for a socket is comprised of multiple slices each with its own PMU.
Access to each
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