Re: [PATCH V4] perf: qcom: Add L3 cache PMU driver

2017-03-23 Thread Agustin Vega-Frias
On 2017-03-23 11:33, Mark Rutland wrote: Hi Agustin, Structurally, this looks good to me. I have a few minor comments below; with those fixed up I think this is ready to merge. Thanks Mark, I'll spin V5 ASAP. Agustin -- Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm

Re: [PATCH V4] perf: qcom: Add L3 cache PMU driver

2017-03-23 Thread Agustin Vega-Frias
On 2017-03-23 11:33, Mark Rutland wrote: Hi Agustin, Structurally, this looks good to me. I have a few minor comments below; with those fixed up I think this is ready to merge. Thanks Mark, I'll spin V5 ASAP. Agustin -- Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm

Re: [PATCH V4] perf: qcom: Add L3 cache PMU driver

2017-03-23 Thread Mark Rutland
Hi Agustin, Structurally, this looks good to me. I have a few minor comments below; with those fixed up I think this is ready to merge. On Fri, Mar 17, 2017 at 10:24:17AM -0400, Agustin Vega-Frias wrote: > +/* > + * General constants > + */ > + > +/* Number of counters on each PMU */ > +#define

Re: [PATCH V4] perf: qcom: Add L3 cache PMU driver

2017-03-23 Thread Mark Rutland
Hi Agustin, Structurally, this looks good to me. I have a few minor comments below; with those fixed up I think this is ready to merge. On Fri, Mar 17, 2017 at 10:24:17AM -0400, Agustin Vega-Frias wrote: > +/* > + * General constants > + */ > + > +/* Number of counters on each PMU */ > +#define

Re: [PATCH V4] perf: qcom: Add L3 cache PMU driver

2017-03-17 Thread Agustin Vega-Frias
On 2017-03-17 10:24, Agustin Vega-Frias wrote: This adds a new dynamic PMU to the Perf Events framework to program and control the L3 cache PMUs in some Qualcomm Technologies SOCs. The driver supports a distributed cache architecture where the overall cache for a socket is comprised of multiple

Re: [PATCH V4] perf: qcom: Add L3 cache PMU driver

2017-03-17 Thread Agustin Vega-Frias
On 2017-03-17 10:24, Agustin Vega-Frias wrote: This adds a new dynamic PMU to the Perf Events framework to program and control the L3 cache PMUs in some Qualcomm Technologies SOCs. The driver supports a distributed cache architecture where the overall cache for a socket is comprised of multiple

[PATCH V4] perf: qcom: Add L3 cache PMU driver

2017-03-17 Thread Agustin Vega-Frias
This adds a new dynamic PMU to the Perf Events framework to program and control the L3 cache PMUs in some Qualcomm Technologies SOCs. The driver supports a distributed cache architecture where the overall cache for a socket is comprised of multiple slices each with its own PMU. Access to each

[PATCH V4] perf: qcom: Add L3 cache PMU driver

2017-03-17 Thread Agustin Vega-Frias
This adds a new dynamic PMU to the Perf Events framework to program and control the L3 cache PMUs in some Qualcomm Technologies SOCs. The driver supports a distributed cache architecture where the overall cache for a socket is comprised of multiple slices each with its own PMU. Access to each