On 4/1/2019 5:11 PM, Stephane Eranian wrote:
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index e2b1447192a8..9378c6b2128f 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -560,6 +560,16 @@ int x86_pmu_hw_config(struct perf_event *event)
On Mon, Apr 1, 2019 at 12:54 PM Liang, Kan wrote:
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> On 4/1/2019 3:18 PM, Stephane Eranian wrote:
> > On Tue, Mar 26, 2019 at 9:11 AM wrote:
> >>
> >> From: Kan Liang
> >>
> >> Starting from Icelake, XMM registers can be collected in PEBS record.
> >> But current code only output the
On 4/1/2019 3:18 PM, Stephane Eranian wrote:
On Tue, Mar 26, 2019 at 9:11 AM wrote:
From: Kan Liang
Starting from Icelake, XMM registers can be collected in PEBS record.
But current code only output the pt_regs.
Add a new struct x86_perf_regs for both pt_regs and xmm_regs.
XMM registers
On Tue, Mar 26, 2019 at 9:11 AM wrote:
>
> From: Kan Liang
>
> Starting from Icelake, XMM registers can be collected in PEBS record.
> But current code only output the pt_regs.
>
> Add a new struct x86_perf_regs for both pt_regs and xmm_regs.
> XMM registers are 128 bit. To simplify the code,
From: Kan Liang
Starting from Icelake, XMM registers can be collected in PEBS record.
But current code only output the pt_regs.
Add a new struct x86_perf_regs for both pt_regs and xmm_regs.
XMM registers are 128 bit. To simplify the code, they are handled like
two different registers, which
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