On Mon, Dec 1, 2014 at 8:09 AM, Jonas Gorski wrote:
> I'm not that firm in interrupt controller terminology, but can this be
> a level 1 interrupt controller if it has a parent interrupt
> controller? Isn't the parent the level 1 interrupt controller? Or
> would the parent then be a level 0 interr
On Fri, Nov 28, 2014 at 5:32 AM, Kevin Cernekee wrote:
> This is the main peripheral IRQ controller on the BCM7xxx MIPS chips;
> it has the following characteristics:
>
> - 64 to 160+ level IRQs
> - Atomic set/clear registers
> - Reasonably predictable register layout (N status words, then N
>
This is the main peripheral IRQ controller on the BCM7xxx MIPS chips;
it has the following characteristics:
- 64 to 160+ level IRQs
- Atomic set/clear registers
- Reasonably predictable register layout (N status words, then N
mask status words, then N mask set words, then N mask clear words)
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