Re: [PATCH V4 1/2] pinctrl: tegra: Add DT binding for io pads control

2016-11-25 Thread Jon Hunter
On 24/11/16 08:38, Laxman Dewangan wrote: > NVIDIA Tegra124 and later SoCs support the multi-voltage level and > low power state of some of its IO pads. The IO pads can work in > the voltage of the 1.8V and 3.3V of IO voltage from IO power rail > sources. Can you fix the above sentence? > When I

Re: [PATCH V4 1/2] pinctrl: tegra: Add DT binding for io pads control

2016-11-25 Thread Laxman Dewangan
On Friday 25 November 2016 02:43 PM, Thierry Reding wrote: * PGP Signed by an unknown key On Thu, Nov 24, 2016 at 02:08:53PM +0530, Laxman Dewangan wrote: + +The DT property of the IO pads must be under the node of pmc i.e. +pmc@7000e400 for Tegra124 onwards. The PMC is at a different address

Re: [PATCH V4 1/2] pinctrl: tegra: Add DT binding for io pads control

2016-11-25 Thread Thierry Reding
On Thu, Nov 24, 2016 at 02:08:53PM +0530, Laxman Dewangan wrote: > NVIDIA Tegra124 and later SoCs support the multi-voltage level and > low power state of some of its IO pads. The IO pads can work in > the voltage of the 1.8V and 3.3V of IO voltage from IO power rail > sources. When IO interfaces a

[PATCH V4 1/2] pinctrl: tegra: Add DT binding for io pads control

2016-11-24 Thread Laxman Dewangan
NVIDIA Tegra124 and later SoCs support the multi-voltage level and low power state of some of its IO pads. The IO pads can work in the voltage of the 1.8V and 3.3V of IO voltage from IO power rail sources. When IO interfaces are not used then IO pads can be configure in low power state to reduce th