Hi Laxman,
[auto build test ERROR on tegra/for-next]
[also build test ERROR on v4.9-rc7 next-20161202]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
Hi Laxman,
[auto build test ERROR on tegra/for-next]
[also build test ERROR on v4.9-rc7 next-20161202]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
On Monday 28 November 2016 02:56 PM, Jon Hunter wrote:
On 25/11/16 17:49, Laxman Dewangan wrote:
In the above dpaux driver, you used the pinctrl framework and its core
functionality for the device tree interfacing and client interfacing.
The same thing I am saying here, we should not avoid
On Monday 28 November 2016 02:56 PM, Jon Hunter wrote:
On 25/11/16 17:49, Laxman Dewangan wrote:
In the above dpaux driver, you used the pinctrl framework and its core
functionality for the device tree interfacing and client interfacing.
The same thing I am saying here, we should not avoid
On 25/11/16 17:45, Laxman Dewangan wrote:
>
> On Friday 25 November 2016 10:56 PM, Jon Hunter wrote:
>> On 25/11/16 09:57, Thierry Reding wrote:
>>> * PGP Signed by an unknown key
>>>
>>> On Thu, Nov 24, 2016 at 02:08:54PM +0530, Laxman Dewangan wrote:
>> ...
>>
diff --git
On 25/11/16 17:45, Laxman Dewangan wrote:
>
> On Friday 25 November 2016 10:56 PM, Jon Hunter wrote:
>> On 25/11/16 09:57, Thierry Reding wrote:
>>> * PGP Signed by an unknown key
>>>
>>> On Thu, Nov 24, 2016 at 02:08:54PM +0530, Laxman Dewangan wrote:
>> ...
>>
diff --git
On 25/11/16 17:49, Laxman Dewangan wrote:
>
> On Friday 25 November 2016 10:59 PM, Jon Hunter wrote:
>> On 25/11/16 12:04, Laxman Dewangan wrote:
>>> Thanks Thierry for review.
>>>
>>> On Friday 25 November 2016 03:27 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On
On 25/11/16 17:49, Laxman Dewangan wrote:
>
> On Friday 25 November 2016 10:59 PM, Jon Hunter wrote:
>> On 25/11/16 12:04, Laxman Dewangan wrote:
>>> Thanks Thierry for review.
>>>
>>> On Friday 25 November 2016 03:27 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On
On Friday 25 November 2016 10:59 PM, Jon Hunter wrote:
On 25/11/16 12:04, Laxman Dewangan wrote:
Thanks Thierry for review.
On Friday 25 November 2016 03:27 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Nov 24, 2016 at 02:08:54PM +0530, Laxman Dewangan wrote:
+
On Friday 25 November 2016 10:59 PM, Jon Hunter wrote:
On 25/11/16 12:04, Laxman Dewangan wrote:
Thanks Thierry for review.
On Friday 25 November 2016 03:27 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Nov 24, 2016 at 02:08:54PM +0530, Laxman Dewangan wrote:
+
On Friday 25 November 2016 10:56 PM, Jon Hunter wrote:
On 25/11/16 09:57, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Nov 24, 2016 at 02:08:54PM +0530, Laxman Dewangan wrote:
...
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra-io-pad.c
On Friday 25 November 2016 10:56 PM, Jon Hunter wrote:
On 25/11/16 09:57, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Nov 24, 2016 at 02:08:54PM +0530, Laxman Dewangan wrote:
...
diff --git a/drivers/pinctrl/tegra/pinctrl-tegra-io-pad.c
On 25/11/16 12:04, Laxman Dewangan wrote:
> Thanks Thierry for review.
>
> On Friday 25 November 2016 03:27 PM, Thierry Reding wrote:
>> * PGP Signed by an unknown key
>>
>> On Thu, Nov 24, 2016 at 02:08:54PM +0530, Laxman Dewangan wrote:
>>> + NVIDIA Tegra124/210 SoC has IO pads which
On 25/11/16 12:04, Laxman Dewangan wrote:
> Thanks Thierry for review.
>
> On Friday 25 November 2016 03:27 PM, Thierry Reding wrote:
>> * PGP Signed by an unknown key
>>
>> On Thu, Nov 24, 2016 at 02:08:54PM +0530, Laxman Dewangan wrote:
>>> + NVIDIA Tegra124/210 SoC has IO pads which
On 25/11/16 09:57, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Thu, Nov 24, 2016 at 02:08:54PM +0530, Laxman Dewangan wrote:
>> NVIDIA Tegra124 and later SoCs support the multi-voltage level and
>> low power state of some of its IO pads. The IO pads can work in
>> the voltage
On 25/11/16 09:57, Thierry Reding wrote:
> * PGP Signed by an unknown key
>
> On Thu, Nov 24, 2016 at 02:08:54PM +0530, Laxman Dewangan wrote:
>> NVIDIA Tegra124 and later SoCs support the multi-voltage level and
>> low power state of some of its IO pads. The IO pads can work in
>> the voltage
Thanks Thierry for review.
On Friday 25 November 2016 03:27 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Nov 24, 2016 at 02:08:54PM +0530, Laxman Dewangan wrote:
+ NVIDIA Tegra124/210 SoC has IO pads which supports multi-voltage
+ level of interfacing and
Thanks Thierry for review.
On Friday 25 November 2016 03:27 PM, Thierry Reding wrote:
* PGP Signed by an unknown key
On Thu, Nov 24, 2016 at 02:08:54PM +0530, Laxman Dewangan wrote:
+ NVIDIA Tegra124/210 SoC has IO pads which supports multi-voltage
+ level of interfacing and
On Thu, Nov 24, 2016 at 02:08:54PM +0530, Laxman Dewangan wrote:
> NVIDIA Tegra124 and later SoCs support the multi-voltage level and
> low power state of some of its IO pads. The IO pads can work in
> the voltage of the 1.8V and 3.3V of IO voltage from IO power rail
> sources. When IO interfaces
On Thu, Nov 24, 2016 at 02:08:54PM +0530, Laxman Dewangan wrote:
> NVIDIA Tegra124 and later SoCs support the multi-voltage level and
> low power state of some of its IO pads. The IO pads can work in
> the voltage of the 1.8V and 3.3V of IO voltage from IO power rail
> sources. When IO interfaces
NVIDIA Tegra124 and later SoCs support the multi-voltage level and
low power state of some of its IO pads. The IO pads can work in
the voltage of the 1.8V and 3.3V of IO voltage from IO power rail
sources. When IO interfaces are not used then IO pads can be
configure in low power state to reduce
NVIDIA Tegra124 and later SoCs support the multi-voltage level and
low power state of some of its IO pads. The IO pads can work in
the voltage of the 1.8V and 3.3V of IO voltage from IO power rail
sources. When IO interfaces are not used then IO pads can be
configure in low power state to reduce
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